From 5d017967fce11dcb71fd735fdd2f3788274e281c Mon Sep 17 00:00:00 2001 From: "Bobby R. Bruce" Date: Wed, 27 Jul 2022 10:10:35 -0700 Subject: [PATCH 01/45] ext: Fix SST Documentation links This documentation links to v21-2 resources. This is incorrect, they should point towards v22-0 resources. This patch fixes this. Change-Id: I0e4868327e0b216619e524c2329f57bbe40d3eae Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/61712 Maintainer: Jason Lowe-Power Reviewed-by: Richard Cooper Tested-by: kokoro Reviewed-by: Jason Lowe-Power --- ext/sst/README.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/ext/sst/README.md b/ext/sst/README.md index dbec200b43..d9bbe85e1b 100644 --- a/ext/sst/README.md +++ b/ext/sst/README.md @@ -62,7 +62,7 @@ See `INSTALL.md`. Downloading the built bootloader containing a Linux Kernel and a workload, ```sh -wget http://dist.gem5.org/dist/v21-2/misc/riscv/bbl-busybox-boot-exit +wget http://dist.gem5.org/dist/v22-0/misc/riscv/bbl-busybox-boot-exit ``` Running the simulation @@ -87,7 +87,7 @@ extract them under the $M5_PATH directory (make sure M5_PATH points to a valid directory): ```sh -wget http://dist.gem5.org/dist/v21-2/arm/aarch-sst-20211207.tar.bz2 +wget http://dist.gem5.org/dist/v22-0/arm/aarch-sst-20211207.tar.bz2 tar -xf aarch-sst-20211207.tar.bz2 # copying bootloaders From fdfa1e38b3aa9c893b1be6ca1014dec49cc3faab Mon Sep 17 00:00:00 2001 From: "Bobby R. Bruce" Date: Tue, 7 Jun 2022 11:24:24 -0700 Subject: [PATCH 02/45] tests: Fix the download test Weekly tests were failing: https://jenkins.gem5.org/job/weekly/56 This was due to the test passing the wrong parameter to the script. Change-Id: Ief810d6b39859129a95fe8a2914e47d21bf879aa Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/60410 Tested-by: kokoro Maintainer: Bobby Bruce Reviewed-by: Bobby Bruce Reviewed-by: Jason Lowe-Power (cherry picked from commit f4f40f44f1996f275015bf26f4911eb5e5315e91) Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/61731 --- tests/gem5/gem5-resources/test_download_resources.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/gem5/gem5-resources/test_download_resources.py b/tests/gem5/gem5-resources/test_download_resources.py index acc72d747d..55b57db095 100644 --- a/tests/gem5/gem5-resources/test_download_resources.py +++ b/tests/gem5/gem5-resources/test_download_resources.py @@ -40,7 +40,7 @@ gem5_verify_config( config=joinpath( config.base_dir, "tests", "gem5", "configs", "download_check.py" ), - config_args=["--resource-directory", resource_path], + config_args=["--download-directory", resource_path], valid_isas=(constants.null_tag,), length=constants.very_long_tag, ) From acfa5da14c8eb49cdffff738358a692f73524659 Mon Sep 17 00:00:00 2001 From: Mahyar Samani Date: Tue, 12 Jul 2022 15:07:39 -0700 Subject: [PATCH 03/45] stdlib: Removing incorrect requires. This change removes call to requires for checking isa_required in AbstractProcessor.__init__() and AbstractGeneratorCore.__init__(). The previous calls would cause incorrect errors when running generators with any isa other than NULL. Change-Id: I303f1e48a7d5649bbe19e0f52ace808225a771c5 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/61289 Tested-by: kokoro Reviewed-by: Jason Lowe-Power Reviewed-by: Bobby Bruce Maintainer: Jason Lowe-Power Maintainer: Bobby Bruce Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/61732 --- .../gem5/components/processors/abstract_generator_core.py | 1 - src/python/gem5/components/processors/abstract_processor.py | 2 -- 2 files changed, 3 deletions(-) diff --git a/src/python/gem5/components/processors/abstract_generator_core.py b/src/python/gem5/components/processors/abstract_generator_core.py index 111a229e35..48a4e818f0 100644 --- a/src/python/gem5/components/processors/abstract_generator_core.py +++ b/src/python/gem5/components/processors/abstract_generator_core.py @@ -54,7 +54,6 @@ class AbstractGeneratorCore(AbstractCore): # TODO: Remove the CPU Type parameter. This not needed. # Jira issue here: https://gem5.atlassian.net/browse/GEM5-1031 super().__init__(CPUTypes.TIMING) - requires(isa_required=ISA.NULL) self.port_end = PortTerminator() @overrides(AbstractCore) diff --git a/src/python/gem5/components/processors/abstract_processor.py b/src/python/gem5/components/processors/abstract_processor.py index 74e78258bb..e6f6395acc 100644 --- a/src/python/gem5/components/processors/abstract_processor.py +++ b/src/python/gem5/components/processors/abstract_processor.py @@ -49,8 +49,6 @@ class AbstractProcessor(SubSystem): assert len(set(core.get_isa() for core in cores)) == 1 self._isa = cores[0].get_isa() - requires(isa_required=self._isa) - self.cores = cores def get_num_cores(self) -> int: From 25f884a0dbb38db528533dedbacaf6144f329982 Mon Sep 17 00:00:00 2001 From: Kaustav Goswami Date: Thu, 14 Jul 2022 01:18:46 -0700 Subject: [PATCH 04/45] stdlib: se_binary_workload exits on work items by default This change makes the method se_binary_workload to exit automatically when work items are encountered during simulation. This makes it similar to the method set_kernel_disk_workload in terms of work items. Change-Id: I8a676e3e174fd65930853b1849e3e0be6a643231 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/61311 Reviewed-by: Bobby Bruce Tested-by: kokoro Maintainer: Bobby Bruce Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/61733 --- .../gem5/components/boards/se_binary_workload.py | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/src/python/gem5/components/boards/se_binary_workload.py b/src/python/gem5/components/boards/se_binary_workload.py index c166add74f..6ff81e7481 100644 --- a/src/python/gem5/components/boards/se_binary_workload.py +++ b/src/python/gem5/components/boards/se_binary_workload.py @@ -39,7 +39,11 @@ class SEBinaryWorkload: AbstractBoard). """ - def set_se_binary_workload(self, binary: AbstractResource) -> None: + def set_se_binary_workload( + self, + binary: AbstractResource, + exit_on_work_items: bool = True + ) -> None: """Set up the system to run a specific binary. **Limitations** @@ -48,6 +52,8 @@ class SEBinaryWorkload: ISA and the simulated ISA are the same. :param binary: The resource encapsulating the binary to be run. + :param exit_on_work_items: Whether the simulation should exit on work + items. True by default. """ # We assume this this is in a multiple-inheritance setup with an @@ -63,3 +69,6 @@ class SEBinaryWorkload: process = Process() process.cmd = [binary.get_local_path()] self.get_processor().get_cores()[0].set_workload(process) + + # Set whether to exit on work items for the se_workload + self.exit_on_work_items = exit_on_work_items From 12d60fbcd7a09a1364a350211296f98386e9bf13 Mon Sep 17 00:00:00 2001 From: Hoa Nguyen Date: Mon, 4 Jul 2022 18:01:28 -0700 Subject: [PATCH 05/45] configs: Fix unconnected PCI port in SST gem5 config PCI Host was added to the HiFive platform here, https://gem5-review.googlesource.com/c/public/gem5/+/59969 This change connects the PCI host to the membus. However, it will not be added to the device tree. Change-Id: I2c1b1049597e5bfd0be467ef2a514d70bc2dd83e Signed-off-by: Hoa Nguyen Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/60989 Reviewed-by: Jason Lowe-Power Tested-by: kokoro Maintainer: Jason Lowe-Power Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/61734 Reviewed-by: Bobby Bruce Maintainer: Bobby Bruce --- configs/example/sst/riscv_fs.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/example/sst/riscv_fs.py b/configs/example/sst/riscv_fs.py index bdbd061120..b5a6cc64b8 100644 --- a/configs/example/sst/riscv_fs.py +++ b/configs/example/sst/riscv_fs.py @@ -93,6 +93,8 @@ def createHiFivePlatform(system): system.platform = HiFive() + system.platform.pci_host.pio = system.membus.mem_side_ports + system.platform.rtc = RiscvRTC(frequency=Frequency("100MHz")) system.platform.clint.int_pin = system.platform.rtc.int_pin From 36c5d05adb450294ca93f41e3aeedd7d6d2d81be Mon Sep 17 00:00:00 2001 From: Ayaz Akram Date: Mon, 18 Jul 2022 22:48:19 -0700 Subject: [PATCH 06/45] mem: Add getAddrRanges in HBMCtrl This change adds a missed function in HBMCtrl to make sure that XBar connected to the controller can see the address ranges covered by both HBM pseudo channels Change-Id: If88edda42b45a66a6517685e091545a5bba6eab9 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/61469 Maintainer: Jason Lowe-Power Tested-by: kokoro Reviewed-by: Jason Lowe-Power Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/61735 Reviewed-by: Bobby Bruce Maintainer: Bobby Bruce --- src/mem/hbm_ctrl.cc | 9 +++++++++ src/mem/hbm_ctrl.hh | 2 ++ 2 files changed, 11 insertions(+) diff --git a/src/mem/hbm_ctrl.cc b/src/mem/hbm_ctrl.cc index 03cfec6c1f..99618c4b5f 100644 --- a/src/mem/hbm_ctrl.cc +++ b/src/mem/hbm_ctrl.cc @@ -488,5 +488,14 @@ HBMCtrl::drainResume() isTimingMode = system()->isTimingMode(); } +AddrRangeList +HBMCtrl::getAddrRanges() +{ + AddrRangeList ranges; + ranges.push_back(pc0Int->getAddrRange()); + ranges.push_back(pc1Int->getAddrRange()); + return ranges; +} + } // namespace memory } // namespace gem5 diff --git a/src/mem/hbm_ctrl.hh b/src/mem/hbm_ctrl.hh index 6c730105f8..9501ff37a0 100644 --- a/src/mem/hbm_ctrl.hh +++ b/src/mem/hbm_ctrl.hh @@ -85,6 +85,8 @@ class HBMCtrl : public MemCtrl */ void pruneBurstTick() override; + AddrRangeList getAddrRanges() override; + public: HBMCtrl(const HBMCtrlParams &p); From 37989aa8903685e5c74d473ce37e41d501c31eca Mon Sep 17 00:00:00 2001 From: Sascha Bischoff Date: Wed, 6 Jul 2022 10:33:36 +0100 Subject: [PATCH 07/45] system-arm: Fix FEAT_PAuth trapping in AArch64 bootloader Now that we start running the bootloader at EL3, we need to setup the SCR_EL3 register so that it doesn't trap any pointer authentication instruction. This is fixing the booting process of Linux kernels making use of FEAT_PAuth Change-Id: I08aa96908dd2c16438448f3cc3c47a1271b2dfa8 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/61069 Reviewed-by: Richard Cooper Tested-by: kokoro Reviewed-by: Andreas Sandberg Maintainer: Andreas Sandberg Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/61736 Maintainer: Giacomo Travaglini Reviewed-by: Giacomo Travaglini Maintainer: Bobby Bruce --- system/arm/bootloader/arm64/boot.S | 2 ++ 1 file changed, 2 insertions(+) diff --git a/system/arm/bootloader/arm64/boot.S b/system/arm/bootloader/arm64/boot.S index 3809f72c2c..50415615d2 100644 --- a/system/arm/bootloader/arm64/boot.S +++ b/system/arm/bootloader/arm64/boot.S @@ -59,6 +59,8 @@ _start: orr x0, x0, #(1 << 0) // Non-secure EL1 orr x0, x0, #(1 << 8) // HVC enable orr x0, x0, #(1 << 10) // 64-bit EL2 + orr x0, x0, #(1 << 16) // Disable FEAT_PAuth traps (APK) + orr x0, x0, #(1 << 17) // Disable FEAT_PAuth traps (API) msr scr_el3, x0 mov x0, #(1 << 8) // Disable SVE trap to EL3 From c0b57d8421238e1ffdeb3d8355d035df5df540f5 Mon Sep 17 00:00:00 2001 From: "Bobby R. Bruce" Date: Wed, 27 Jul 2022 10:41:24 -0700 Subject: [PATCH 08/45] misc: Update version info to v22.0.0.2 Change-Id: I102ffac04547a5fab49d6d87b0a53f6cf0b44395 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/61737 Reviewed-by: Bobby Bruce Maintainer: Bobby Bruce Tested-by: kokoro --- src/Doxyfile | 2 +- src/base/version.cc | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/Doxyfile b/src/Doxyfile index a49de0f124..c8bde04cbb 100644 --- a/src/Doxyfile +++ b/src/Doxyfile @@ -31,7 +31,7 @@ PROJECT_NAME = gem5 # This could be handy for archiving the generated documentation or # if some version control system is used. -PROJECT_NUMBER = v22.0.0.1 +PROJECT_NUMBER = v22.0.0.2 # The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) # base path where the generated documentation will be put. diff --git a/src/base/version.cc b/src/base/version.cc index 33b0fd06db..fa29d1bee3 100644 --- a/src/base/version.cc +++ b/src/base/version.cc @@ -32,6 +32,6 @@ namespace gem5 /** * @ingroup api_base_utils */ -const char *gem5Version = "22.0.0.1"; +const char *gem5Version = "22.0.0.2"; } // namespace gem5 From 1d03f6de941520860c673b5f7954c82a46e8b191 Mon Sep 17 00:00:00 2001 From: "Bobby R. Bruce" Date: Wed, 27 Jul 2022 11:06:57 -0700 Subject: [PATCH 09/45] misc: Update RELEASE-NOTES.md for v22.0.0.2 Change-Id: I9a37782b097be93f871b37c0520ad282cb90a584 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/61738 Maintainer: Bobby Bruce Tested-by: kokoro Reviewed-by: Bobby Bruce --- RELEASE-NOTES.md | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/RELEASE-NOTES.md b/RELEASE-NOTES.md index 881285f695..2353a96a67 100644 --- a/RELEASE-NOTES.md +++ b/RELEASE-NOTES.md @@ -1,3 +1,18 @@ +# Version 22.0.0.2 + +**[HOTFIX]** This hotfix contains a set of critical fixes to be applied to gem5 v22.0. +This hotfix: + +- Fixes the ARM booting of Linux kernels making use of FEAT_PAuth. +- Removes incorrect `requires` functions in AbstractProcessor and AbstractGeneratorCore. +These `requires` were causing errors when running generators with any ISA other than NULL. +- Fixes the standard library's `set_se_binary_workload` function to exit on Exit Events (work items) by default. +- Connects a previously unconnected PCI port in the example SST RISC-V config to the membus. +- Updates the SST-gem5 README with the correct download links. +- Adds a `getAddrRanges` function to the `HBMCtrl`. +This ensures the XBar connected to the controller can see the address ranges covered by both pseudo channels. +- Fixes test_download_resources.py so the correct parameter is passed to the download test script. + # Version 22.0.0.1 **[HOTFIX]** Fixes relative import in "src/python/gem5/components/processors/simple_core.py". From f172c41c68c71a565571a3edd5b0a405d00449e5 Mon Sep 17 00:00:00 2001 From: Jasjeet Rangi Date: Mon, 7 Nov 2022 15:09:24 -0800 Subject: [PATCH 10/45] stdlib: Fix get_isa_from_str() exception behavior in isas.py When given an input string that does not match any valid ISA, the get_isa_from_str() function should call get_isas_str_set() to to print the valid ISA strings in the exception. The current behavior is to recursively call get_isa_from_str() with no input, which prevents the correct exception from being raised. This change causes the correct exception to be raised for invalid inputs. Change-Id: I92bfe862bbd99ce0b63bfc124e539fab3b175e0c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65411 Reviewed-by: Jason Lowe-Power Maintainer: Bobby Bruce Reviewed-by: Bobby Bruce Tested-by: kokoro --- src/python/gem5/isas.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/python/gem5/isas.py b/src/python/gem5/isas.py index c904c9d227..84f02b87e7 100644 --- a/src/python/gem5/isas.py +++ b/src/python/gem5/isas.py @@ -81,7 +81,7 @@ def get_isa_from_str(input: str) -> ISA: return isa valid_isas_str_list = str() - for isa_str in get_isa_from_str(): + for isa_str in get_isas_str_set(): valid_isas_str_list += f"{os.linesep}{isa_str}" raise Exception( From 56c359c41ba4809998cff3ec14d791400c8ac0f3 Mon Sep 17 00:00:00 2001 From: Matthew Poremba Date: Tue, 8 Nov 2022 14:24:32 -0800 Subject: [PATCH 11/45] dev-amdgpu: Handle ring buffer wrap for PM4 queue Change-Id: I27bc274327838add709423b072d437c4e727a714 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65431 Maintainer: Matt Sinclair Tested-by: kokoro Reviewed-by: Matt Sinclair (cherry picked from commit 623e2d3dac3e75c67b4e1b8f6a7113f0ab376960) Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65452 Maintainer: Bobby Bruce Reviewed-by: Matthew Poremba Reviewed-by: Bobby Bruce --- src/dev/amdgpu/pm4_mmio.hh | 1 + src/dev/amdgpu/pm4_packet_processor.cc | 13 +++++++++++-- src/dev/amdgpu/pm4_packet_processor.hh | 1 + src/dev/amdgpu/pm4_queues.hh | 7 +++++-- 4 files changed, 18 insertions(+), 4 deletions(-) diff --git a/src/dev/amdgpu/pm4_mmio.hh b/src/dev/amdgpu/pm4_mmio.hh index a3ce5f14e5..3801223175 100644 --- a/src/dev/amdgpu/pm4_mmio.hh +++ b/src/dev/amdgpu/pm4_mmio.hh @@ -60,6 +60,7 @@ namespace gem5 #define mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI 0x1251 #define mmCP_HQD_PQ_WPTR_POLL_ADDR 0x1252 #define mmCP_HQD_PQ_WPTR_POLL_ADDR_HI 0x1253 +#define mmCP_HQD_PQ_CONTROL 0x1256 #define mmCP_HQD_IB_CONTROL 0x125a #define mmCP_HQD_PQ_WPTR_LO 0x127b #define mmCP_HQD_PQ_WPTR_HI 0x127c diff --git a/src/dev/amdgpu/pm4_packet_processor.cc b/src/dev/amdgpu/pm4_packet_processor.cc index 404beab16c..c8e63207f4 100644 --- a/src/dev/amdgpu/pm4_packet_processor.cc +++ b/src/dev/amdgpu/pm4_packet_processor.cc @@ -147,8 +147,8 @@ PM4PacketProcessor::newQueue(QueueDesc *mqd, Addr offset, gpuDevice->setDoorbellType(offset, qt); DPRINTF(PM4PacketProcessor, "New PM4 queue %d, base: %p offset: %p, me: " - "%d, pipe %d queue: %d\n", id, q->base(), q->offset(), q->me(), - q->pipe(), q->queue()); + "%d, pipe %d queue: %d size: %d\n", id, q->base(), q->offset(), + q->me(), q->pipe(), q->queue(), q->size()); } void @@ -784,6 +784,9 @@ PM4PacketProcessor::writeMMIO(PacketPtr pkt, Addr mmio_offset) case mmCP_HQD_PQ_WPTR_POLL_ADDR_HI: setHqdPqWptrPollAddrHi(pkt->getLE()); break; + case mmCP_HQD_PQ_CONTROL: + setHqdPqControl(pkt->getLE()); + break; case mmCP_HQD_IB_CONTROL: setHqdIbCtrl(pkt->getLE()); break; @@ -905,6 +908,12 @@ PM4PacketProcessor::setHqdPqWptrPollAddrHi(uint32_t data) kiq.hqd_pq_wptr_poll_addr_hi = data; } +void +PM4PacketProcessor::setHqdPqControl(uint32_t data) +{ + kiq.hqd_pq_control = data; +} + void PM4PacketProcessor::setHqdIbCtrl(uint32_t data) { diff --git a/src/dev/amdgpu/pm4_packet_processor.hh b/src/dev/amdgpu/pm4_packet_processor.hh index 48066713a5..4617a21a06 100644 --- a/src/dev/amdgpu/pm4_packet_processor.hh +++ b/src/dev/amdgpu/pm4_packet_processor.hh @@ -171,6 +171,7 @@ class PM4PacketProcessor : public DmaVirtDevice void setHqdPqRptrReportAddrHi(uint32_t data); void setHqdPqWptrPollAddr(uint32_t data); void setHqdPqWptrPollAddrHi(uint32_t data); + void setHqdPqControl(uint32_t data); void setHqdIbCtrl(uint32_t data); void setRbVmid(uint32_t data); void setRbCntl(uint32_t data); diff --git a/src/dev/amdgpu/pm4_queues.hh b/src/dev/amdgpu/pm4_queues.hh index 19973b113e..8b6626d176 100644 --- a/src/dev/amdgpu/pm4_queues.hh +++ b/src/dev/amdgpu/pm4_queues.hh @@ -396,14 +396,14 @@ class PM4Queue rptr() { if (ib()) return q->ibBase + q->ibRptr; - else return q->base + q->rptr; + else return q->base + (q->rptr % size()); } Addr wptr() { if (ib()) return q->ibBase + _ibWptr; - else return q->base + _wptr; + else return q->base + (_wptr % size()); } Addr @@ -470,6 +470,9 @@ class PM4Queue uint32_t pipe() { return _pkt.pipe; } uint32_t queue() { return _pkt.queueSlot; } bool privileged() { return _pkt.queueSel == 0 ? 1 : 0; } + + // Same computation as processMQD. See comment there for details. + uint64_t size() { return 4UL << ((q->hqd_pq_control & 0x3f) + 1); } }; } // namespace gem5 From 729a9399e4831865459f56da9701e31710dc55fe Mon Sep 17 00:00:00 2001 From: Matthew Poremba Date: Tue, 8 Nov 2022 19:58:07 -0800 Subject: [PATCH 12/45] arch-vega: Fix SOPK instruction sign extends See: https://gem5-review.googlesource.com/c/public/gem5/+/37495 Same patch but for vega. This fixes issues with lulesh and probably rodinia - heartwall as well in fullsystem. Change-Id: I3af36bb9b60d32dc96cc3b439bb1167be1b0945d Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65432 Reviewed-by: Matt Sinclair Maintainer: Matt Sinclair Tested-by: kokoro (cherry picked from commit 8693d725e202002893aafc4ac814bfa87c86ae76) Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65453 Maintainer: Bobby Bruce Reviewed-by: Bobby Bruce Reviewed-by: Matthew Poremba --- src/arch/amdgpu/vega/insts/instructions.cc | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/src/arch/amdgpu/vega/insts/instructions.cc b/src/arch/amdgpu/vega/insts/instructions.cc index 76bb8aad49..f5b08b7ce1 100644 --- a/src/arch/amdgpu/vega/insts/instructions.cc +++ b/src/arch/amdgpu/vega/insts/instructions.cc @@ -1553,7 +1553,7 @@ namespace VegaISA void Inst_SOPK__S_MOVK_I32::execute(GPUDynInstPtr gpuDynInst) { - ScalarRegI32 simm16 = (ScalarRegI32)instData.SIMM16; + ScalarRegI32 simm16 = (ScalarRegI32)sext<16>(instData.SIMM16); ScalarOperandI32 sdst(gpuDynInst, instData.SDST); sdst = simm16; @@ -1579,7 +1579,7 @@ namespace VegaISA void Inst_SOPK__S_CMOVK_I32::execute(GPUDynInstPtr gpuDynInst) { - ScalarRegI32 simm16 = (ScalarRegI32)instData.SIMM16; + ScalarRegI32 simm16 = (ScalarRegI32)sext<16>(instData.SIMM16); ScalarOperandI32 sdst(gpuDynInst, instData.SDST); ConstScalarOperandU32 scc(gpuDynInst, REG_SCC); @@ -1607,7 +1607,7 @@ namespace VegaISA void Inst_SOPK__S_CMPK_EQ_I32::execute(GPUDynInstPtr gpuDynInst) { - ScalarRegI32 simm16 = (ScalarRegI32)instData.SIMM16; + ScalarRegI32 simm16 = (ScalarRegI32)sext<16>(instData.SIMM16); ConstScalarOperandI32 src(gpuDynInst, instData.SDST); ScalarOperandU32 scc(gpuDynInst, REG_SCC); @@ -1634,7 +1634,7 @@ namespace VegaISA void Inst_SOPK__S_CMPK_LG_I32::execute(GPUDynInstPtr gpuDynInst) { - ScalarRegI32 simm16 = (ScalarRegI32)instData.SIMM16; + ScalarRegI32 simm16 = (ScalarRegI32)sext<16>(instData.SIMM16); ConstScalarOperandI32 src(gpuDynInst, instData.SDST); ScalarOperandU32 scc(gpuDynInst, REG_SCC); @@ -1661,7 +1661,7 @@ namespace VegaISA void Inst_SOPK__S_CMPK_GT_I32::execute(GPUDynInstPtr gpuDynInst) { - ScalarRegI32 simm16 = (ScalarRegI32)instData.SIMM16; + ScalarRegI32 simm16 = (ScalarRegI32)sext<16>(instData.SIMM16); ConstScalarOperandI32 src(gpuDynInst, instData.SDST); ScalarOperandU32 scc(gpuDynInst, REG_SCC); @@ -1688,7 +1688,7 @@ namespace VegaISA void Inst_SOPK__S_CMPK_GE_I32::execute(GPUDynInstPtr gpuDynInst) { - ScalarRegI32 simm16 = (ScalarRegI32)instData.SIMM16; + ScalarRegI32 simm16 = (ScalarRegI32)sext<16>(instData.SIMM16); ConstScalarOperandI32 src(gpuDynInst, instData.SDST); ScalarOperandU32 scc(gpuDynInst, REG_SCC); @@ -1715,7 +1715,7 @@ namespace VegaISA void Inst_SOPK__S_CMPK_LT_I32::execute(GPUDynInstPtr gpuDynInst) { - ScalarRegI32 simm16 = (ScalarRegI32)instData.SIMM16; + ScalarRegI32 simm16 = (ScalarRegI32)sext<16>(instData.SIMM16); ConstScalarOperandI32 src(gpuDynInst, instData.SDST); ScalarOperandU32 scc(gpuDynInst, REG_SCC); @@ -1742,7 +1742,7 @@ namespace VegaISA void Inst_SOPK__S_CMPK_LE_I32::execute(GPUDynInstPtr gpuDynInst) { - ScalarRegI32 simm16 = (ScalarRegI32)instData.SIMM16; + ScalarRegI32 simm16 = (ScalarRegI32)sext<16>(instData.SIMM16); ConstScalarOperandI32 src(gpuDynInst, instData.SDST); ScalarOperandU32 scc(gpuDynInst, REG_SCC); @@ -1939,7 +1939,7 @@ namespace VegaISA src.read(); - sdst = src.rawData() + (ScalarRegI32)simm16; + sdst = src.rawData() + (ScalarRegI32)sext<16>(simm16); scc = (bits(src.rawData(), 31) == bits(simm16, 15) && bits(src.rawData(), 31) != bits(sdst.rawData(), 31)) ? 1 : 0; @@ -1969,7 +1969,7 @@ namespace VegaISA src.read(); - sdst = src.rawData() * (ScalarRegI32)simm16; + sdst = src.rawData() * (ScalarRegI32)sext<16>(simm16); sdst.write(); } // execute From 04767ddc620c6bc6bf04aca54b1b7fb08a149500 Mon Sep 17 00:00:00 2001 From: Matthew Poremba Date: Mon, 7 Nov 2022 16:28:15 -0800 Subject: [PATCH 13/45] dev-amdgpu: Fix SDMA ring buffer wrap around The current SDMA wrap around handling only considers the ring buffer location as seen by the GPU. Eventually when the end of the SDMA ring buffer is reached, the driver waits until the rptr written back to the host catches up to what the driver sees before wrapping around back to the beginning of the buffer. This writeback currently does not happen at all, causing hangs for applications with a lot of SDMA commands. This changeset first fixes the sizes of the queues, especially RLC queues, so that the wrap around occurs in the correct place. Second, we now store the rptr writeback address and the absoluate (unwrapped) rptr value in each SDMA queue. The absolulte rptr is what the driver sends to the device and what it expects to be written back. This was tested with an application which basically does a few hundred thousand hipMemcpy() calls in a loop. It should also fix the issue with pannotia BC in fullsystem mode. Change-Id: I53ebdcc6b02fb4eb4da435c9a509544066a97069 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65351 Maintainer: Jason Lowe-Power Tested-by: kokoro Reviewed-by: Jason Lowe-Power Reviewed-by: Matt Sinclair Maintainer: Matt Sinclair (cherry picked from commit c8d687b05c803e3b358014e7f729a5700a003552) Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65451 Maintainer: Bobby Bruce Reviewed-by: Bobby Bruce Reviewed-by: Matthew Poremba --- src/dev/amdgpu/pm4_packet_processor.cc | 14 ++++++++---- src/dev/amdgpu/sdma_engine.cc | 30 ++++++++++++++++++++------ src/dev/amdgpu/sdma_engine.hh | 18 ++++++++++++---- 3 files changed, 47 insertions(+), 15 deletions(-) diff --git a/src/dev/amdgpu/pm4_packet_processor.cc b/src/dev/amdgpu/pm4_packet_processor.cc index c8e63207f4..f78f8333a6 100644 --- a/src/dev/amdgpu/pm4_packet_processor.cc +++ b/src/dev/amdgpu/pm4_packet_processor.cc @@ -441,12 +441,17 @@ void PM4PacketProcessor::processSDMAMQD(PM4MapQueues *pkt, PM4Queue *q, Addr addr, SDMAQueueDesc *mqd, uint16_t vmid) { + uint32_t rlc_size = 4UL << bits(mqd->sdmax_rlcx_rb_cntl, 6, 1); + Addr rptr_wb_addr = mqd->sdmax_rlcx_rb_rptr_addr_hi; + rptr_wb_addr <<= 32; + rptr_wb_addr |= mqd->sdmax_rlcx_rb_rptr_addr_lo; + DPRINTF(PM4PacketProcessor, "SDMAMQD: rb base: %#lx rptr: %#x/%#x wptr: " - "%#x/%#x ib: %#x/%#x size: %d ctrl: %#x\n", mqd->rb_base, - mqd->sdmax_rlcx_rb_rptr, mqd->sdmax_rlcx_rb_rptr_hi, + "%#x/%#x ib: %#x/%#x size: %d ctrl: %#x rptr wb addr: %#lx\n", + mqd->rb_base, mqd->sdmax_rlcx_rb_rptr, mqd->sdmax_rlcx_rb_rptr_hi, mqd->sdmax_rlcx_rb_wptr, mqd->sdmax_rlcx_rb_wptr_hi, mqd->sdmax_rlcx_ib_base_lo, mqd->sdmax_rlcx_ib_base_hi, - mqd->sdmax_rlcx_ib_size, mqd->sdmax_rlcx_rb_cntl); + rlc_size, mqd->sdmax_rlcx_rb_cntl, rptr_wb_addr); // Engine 2 points to SDMA0 while engine 3 points to SDMA1 assert(pkt->engineSel == 2 || pkt->engineSel == 3); @@ -454,7 +459,8 @@ PM4PacketProcessor::processSDMAMQD(PM4MapQueues *pkt, PM4Queue *q, Addr addr, // Register RLC queue with SDMA sdma_eng->registerRLCQueue(pkt->doorbellOffset << 2, - mqd->rb_base << 8); + mqd->rb_base << 8, rlc_size, + rptr_wb_addr); // Register doorbell with GPU device gpuDevice->setSDMAEngine(pkt->doorbellOffset << 2, sdma_eng); diff --git a/src/dev/amdgpu/sdma_engine.cc b/src/dev/amdgpu/sdma_engine.cc index e9a4c176d8..59c5027c85 100644 --- a/src/dev/amdgpu/sdma_engine.cc +++ b/src/dev/amdgpu/sdma_engine.cc @@ -161,7 +161,8 @@ SDMAEngine::translate(Addr vaddr, Addr size) } void -SDMAEngine::registerRLCQueue(Addr doorbell, Addr rb_base) +SDMAEngine::registerRLCQueue(Addr doorbell, Addr rb_base, uint32_t size, + Addr rptr_wb_addr) { // Get first free RLC if (!rlc0.valid()) { @@ -171,19 +172,19 @@ SDMAEngine::registerRLCQueue(Addr doorbell, Addr rb_base) rlc0.base(rb_base); rlc0.rptr(0); rlc0.wptr(0); + rlc0.rptrWbAddr(rptr_wb_addr); rlc0.processing(false); - // TODO: size - I think pull from MQD 2^rb_cntrl[6:1]-1 - rlc0.size(1024*1024); + rlc0.size(size); } else if (!rlc1.valid()) { DPRINTF(SDMAEngine, "Doorbell %lx mapped to RLC1\n", doorbell); rlcInfo[1] = doorbell; rlc1.valid(true); rlc1.base(rb_base); - rlc1.rptr(1); - rlc1.wptr(1); + rlc1.rptr(0); + rlc1.wptr(0); + rlc1.rptrWbAddr(rptr_wb_addr); rlc1.processing(false); - // TODO: size - I think pull from MQD 2^rb_cntrl[6:1]-1 - rlc1.size(1024*1024); + rlc1.size(size); } else { panic("No free RLCs. Check they are properly unmapped."); } @@ -291,6 +292,17 @@ SDMAEngine::decodeNext(SDMAQueue *q) { decodeHeader(q, header); }); dmaReadVirt(q->rptr(), sizeof(uint32_t), cb, &cb->dmaBuffer); } else { + // The driver expects the rptr to be written back to host memory + // periodically. In simulation, we writeback rptr after each burst of + // packets from a doorbell, rather than using the cycle count which + // is not accurate in all simulation settings (e.g., KVM). + DPRINTF(SDMAEngine, "Writing rptr %#lx back to host addr %#lx\n", + q->globalRptr(), q->rptrWbAddr()); + if (q->rptrWbAddr()) { + auto cb = new DmaVirtCallback( + [ = ](const uint64_t &) { }, q->globalRptr()); + dmaWriteVirt(q->rptrWbAddr(), sizeof(Addr), cb, &cb->dmaBuffer); + } q->processing(false); if (q->parent()) { DPRINTF(SDMAEngine, "SDMA switching queues\n"); @@ -1158,6 +1170,7 @@ SDMAEngine::setGfxRptrLo(uint32_t data) { gfxRptr = insertBits(gfxRptr, 31, 0, 0); gfxRptr |= data; + gfx.rptrWbAddr(getGARTAddr(gfxRptr)); } void @@ -1165,6 +1178,7 @@ SDMAEngine::setGfxRptrHi(uint32_t data) { gfxRptr = insertBits(gfxRptr, 63, 32, 0); gfxRptr |= ((uint64_t)data) << 32; + gfx.rptrWbAddr(getGARTAddr(gfxRptr)); } void @@ -1236,6 +1250,7 @@ SDMAEngine::setPageRptrLo(uint32_t data) { pageRptr = insertBits(pageRptr, 31, 0, 0); pageRptr |= data; + page.rptrWbAddr(getGARTAddr(pageRptr)); } void @@ -1243,6 +1258,7 @@ SDMAEngine::setPageRptrHi(uint32_t data) { pageRptr = insertBits(pageRptr, 63, 32, 0); pageRptr |= ((uint64_t)data) << 32; + page.rptrWbAddr(getGARTAddr(pageRptr)); } void diff --git a/src/dev/amdgpu/sdma_engine.hh b/src/dev/amdgpu/sdma_engine.hh index 6fe7a8e565..d0afaf7a4a 100644 --- a/src/dev/amdgpu/sdma_engine.hh +++ b/src/dev/amdgpu/sdma_engine.hh @@ -58,6 +58,8 @@ class SDMAEngine : public DmaVirtDevice Addr _rptr; Addr _wptr; Addr _size; + Addr _rptr_wb_addr = 0; + Addr _global_rptr = 0; bool _valid; bool _processing; SDMAQueue *_parent; @@ -72,6 +74,8 @@ class SDMAEngine : public DmaVirtDevice Addr wptr() { return _base + _wptr; } Addr getWptr() { return _wptr; } Addr size() { return _size; } + Addr rptrWbAddr() { return _rptr_wb_addr; } + Addr globalRptr() { return _global_rptr; } bool valid() { return _valid; } bool processing() { return _processing; } SDMAQueue* parent() { return _parent; } @@ -82,22 +86,27 @@ class SDMAEngine : public DmaVirtDevice void incRptr(uint32_t value) { - //assert((_rptr + value) <= (_size << 1)); _rptr = (_rptr + value) % _size; + _global_rptr += value; } - void rptr(Addr value) { _rptr = value; } + void + rptr(Addr value) + { + _rptr = value; + _global_rptr = value; + } void setWptr(Addr value) { - //assert(value <= (_size << 1)); _wptr = value % _size; } void wptr(Addr value) { _wptr = value; } void size(Addr value) { _size = value; } + void rptrWbAddr(Addr value) { _rptr_wb_addr = value; } void valid(bool v) { _valid = v; } void processing(bool value) { _processing = value; } void parent(SDMAQueue* q) { _parent = q; } @@ -268,7 +277,8 @@ class SDMAEngine : public DmaVirtDevice /** * Methods for RLC queues */ - void registerRLCQueue(Addr doorbell, Addr rb_base); + void registerRLCQueue(Addr doorbell, Addr rb_base, uint32_t size, + Addr rptr_wb_addr); void unregisterRLCQueue(Addr doorbell); void deallocateRLCQueues(); From 98f3d779b73ca9d8ebeb46e2cd6e312bbc20a3f3 Mon Sep 17 00:00:00 2001 From: "Bobby R. Bruce" Date: Thu, 10 Nov 2022 17:07:11 -0800 Subject: [PATCH 14/45] arch-x86: X86ISA default vector_string to HygonGenuine This commit, https://gem5-review.googlesource.com/c/public/gem5/+/64831, changed the default 'vendor_string' for the 'X86ISA' SimObject from 'M5 Simulator' and 'AuthenticAMD'. Unforunately due to an issue highlighted here: https://gem5.atlassian.net/browse/GEM5-1300 we cannot use the 'AuthenticAMD'. Therefore, this change updates the default vector_string to HygonGenuine. The HygonGenuine is simple but works. Change-Id: I21421da8ae73e76d9daaf2fdd0b3238d5b309172 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65492 Tested-by: kokoro Maintainer: Bobby Bruce Reviewed-by: Bobby Bruce Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65611 Reviewed-by: Matt Sinclair --- src/arch/x86/X86ISA.py | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/src/arch/x86/X86ISA.py b/src/arch/x86/X86ISA.py index 2760b7672d..bb72c415e9 100644 --- a/src/arch/x86/X86ISA.py +++ b/src/arch/x86/X86ISA.py @@ -42,6 +42,15 @@ class X86ISA(BaseISA): cxx_class = "gem5::X86ISA::ISA" cxx_header = "arch/x86/isa.hh" + # Here we set the default vector string to "HygonGenuine". Previously this + # "M5 Simulator" but due to stricter checks in newer versions of GLIBC, + # the CPUID is checked for the required features. As "M5 Simulator" is not + # genuine CPUID, an error is returned. This change + # https://gem5-review.googlesource.com/c/public/gem5/+/64831 changed this + # to "GenuineAMD" but due to issues with booting the Linux Kernel using + # this vector string (highlighted here: + # https://gem5.atlassian.net/browse/GEM5-1300) we opted to use + # "HygonGenuine" instead. vendor_string = Param.String( - "AuthenticAMD", "Vendor string for CPUID instruction" + "HygonGenuine", "Vendor string for CPUID instruction" ) From 9696cb517a6b5be7f3d006c1136853f74123cce5 Mon Sep 17 00:00:00 2001 From: "Bobby R. Bruce" Date: Thu, 17 Nov 2022 15:48:34 -0800 Subject: [PATCH 15/45] arch-arm: Revert 'Setup TC/ISA at construction time..' MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reverts: dd2f1fb2f8520849f10fc25fc5eab5beaa90a7d4 https://gem5-review.googlesource.com/c/public/gem5/+/65174 and 47bd56ee71ba1d684138365e7123aa779989ba1d https://gem5-review.googlesource.com/c/public/gem5/+/65291 The 47bd56ee change resulted in the `SuiteUID:tests/gem5/fs/linux/arm/test.py:realview-switcheroo-noncaching-timing-ALL-x86_64-opt` nightly test stalling. This behavior can be reproduced with: ``` ./build/ALL/gem5.opt tests/gem5/fs/linux/arm/run.py tests/gem5/configs/realview-switcheroo-noncaching-timing.py tests/gem5/resources/arm “$(pwd)” ``` The subsequent change, dd2f1fb2, must be reverted for this change to be reverted. Change-Id: I6fed74f33d013f321b93cf1a73eee404cb87ce18 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65732 Reviewed-by: Jason Lowe-Power Maintainer: Bobby Bruce Tested-by: kokoro Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65971 Reviewed-by: Bobby Bruce --- src/arch/arm/isa.cc | 20 +++++++++++--------- src/dev/arm/gic_v3.cc | 2 +- src/dev/arm/gic_v3_cpu_interface.cc | 17 +++++++++++------ src/dev/arm/gic_v3_cpu_interface.hh | 9 +++++---- 4 files changed, 28 insertions(+), 20 deletions(-) diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index fd19f721b2..a30fd94596 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -523,6 +523,16 @@ ISA::setupThreadContext() return; selfDebug->init(tc); + + Gicv3 *gicv3 = dynamic_cast(system->getGIC()); + if (!gicv3) + return; + + if (!gicv3CpuInterface) + gicv3CpuInterface.reset(gicv3->getCPUInterface(tc->contextId())); + + gicv3CpuInterface->setISA(this); + gicv3CpuInterface->setThreadContext(tc); } void @@ -1998,15 +2008,7 @@ ISA::getGenericTimer() BaseISADevice & ISA::getGICv3CPUInterface() { - if (gicv3CpuInterface) - return *gicv3CpuInterface.get(); - - assert(system); - Gicv3 *gicv3 = dynamic_cast(system->getGIC()); - panic_if(!gicv3, "The system does not have a GICv3 irq controller\n"); - - gicv3CpuInterface.reset(gicv3->getCPUInterface(tc->contextId())); - + panic_if(!gicv3CpuInterface, "GICV3 cpu interface is not registered!"); return *gicv3CpuInterface.get(); } diff --git a/src/dev/arm/gic_v3.cc b/src/dev/arm/gic_v3.cc index e14d1f2bef..dde3818b07 100644 --- a/src/dev/arm/gic_v3.cc +++ b/src/dev/arm/gic_v3.cc @@ -147,7 +147,7 @@ Gicv3::init() for (int i = 0; i < threads; i++) { redistributors[i] = new Gicv3Redistributor(this, i); - cpuInterfaces[i] = new Gicv3CPUInterface(this, sys->threads[i]); + cpuInterfaces[i] = new Gicv3CPUInterface(this, i); } distRange = RangeSize(params().dist_addr, diff --git a/src/dev/arm/gic_v3_cpu_interface.cc b/src/dev/arm/gic_v3_cpu_interface.cc index a11dd9b8ed..0e1dbaa04b 100644 --- a/src/dev/arm/gic_v3_cpu_interface.cc +++ b/src/dev/arm/gic_v3_cpu_interface.cc @@ -55,19 +55,15 @@ using namespace ArmISA; const uint8_t Gicv3CPUInterface::GIC_MIN_BPR; const uint8_t Gicv3CPUInterface::GIC_MIN_BPR_NS; -Gicv3CPUInterface::Gicv3CPUInterface(Gicv3 * gic, ThreadContext *_tc) +Gicv3CPUInterface::Gicv3CPUInterface(Gicv3 * gic, uint32_t cpu_id) : BaseISADevice(), gic(gic), redistributor(nullptr), distributor(nullptr), - tc(_tc), - maintenanceInterrupt(gic->params().maint_int->get(tc)), - cpuId(tc->contextId()) + cpuId(cpu_id) { hppi.prio = 0xff; hppi.intid = Gicv3::INTID_SPURIOUS; - - setISA(static_cast(tc->getIsaPtr())); } void @@ -84,6 +80,15 @@ Gicv3CPUInterface::resetHppi(uint32_t intid) hppi.prio = 0xff; } +void +Gicv3CPUInterface::setThreadContext(ThreadContext *_tc) +{ + tc = _tc; + maintenanceInterrupt = gic->params().maint_int->get(tc); + fatal_if(maintenanceInterrupt->num() >= redistributor->irqPending.size(), + "Invalid maintenance interrupt number\n"); +} + bool Gicv3CPUInterface::getHCREL2FMO() const { diff --git a/src/dev/arm/gic_v3_cpu_interface.hh b/src/dev/arm/gic_v3_cpu_interface.hh index c39fab7647..e860373fb5 100644 --- a/src/dev/arm/gic_v3_cpu_interface.hh +++ b/src/dev/arm/gic_v3_cpu_interface.hh @@ -68,11 +68,11 @@ class Gicv3CPUInterface : public ArmISA::BaseISADevice, public Serializable Gicv3 * gic; Gicv3Redistributor * redistributor; Gicv3Distributor * distributor; - - ThreadContext *tc; - ArmInterruptPin *maintenanceInterrupt; uint32_t cpuId; + ArmInterruptPin *maintenanceInterrupt; + ThreadContext *tc; + BitUnion64(ICC_CTLR_EL1) Bitfield<63, 20> res0_3; Bitfield<19> ExtRange; @@ -359,7 +359,7 @@ class Gicv3CPUInterface : public ArmISA::BaseISADevice, public Serializable void setBankedMiscReg(ArmISA::MiscRegIndex misc_reg, RegVal val) const; public: - Gicv3CPUInterface(Gicv3 * gic, ThreadContext *tc); + Gicv3CPUInterface(Gicv3 * gic, uint32_t cpu_id); void init(); @@ -369,6 +369,7 @@ class Gicv3CPUInterface : public ArmISA::BaseISADevice, public Serializable public: // BaseISADevice RegVal readMiscReg(int misc_reg) override; void setMiscReg(int misc_reg, RegVal val) override; + void setThreadContext(ThreadContext *tc) override; }; } // namespace gem5 From f34f582dcfe80e69c0c4e793bb4b8d9664acf27e Mon Sep 17 00:00:00 2001 From: "Bobby R. Bruce" Date: Mon, 21 Nov 2022 11:52:57 -0800 Subject: [PATCH 16/45] stdlib,configs: Update riscvmatched-fs example docstring This documentation string provided in the "config/example/gem5_library/riscvmatched-fs.py" was minimal. This patch adds more detail. Change-Id: I0f203ea6952fc72a078594d7c30853bd426017ff Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65851 Tested-by: kokoro Reviewed-by: Bobby Bruce Maintainer: Bobby Bruce Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65972 --- configs/example/gem5_library/riscvmatched-fs.py | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/configs/example/gem5_library/riscvmatched-fs.py b/configs/example/gem5_library/riscvmatched-fs.py index da47a4be6c..1ed78e81a3 100644 --- a/configs/example/gem5_library/riscvmatched-fs.py +++ b/configs/example/gem5_library/riscvmatched-fs.py @@ -25,8 +25,8 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. """ -This gem5 configuration script runs a full system Ubuntu image, Linux -kernel and calls m5 exit after the kernel is loaded. +This gem5 configuration script runs the RISCVMatchedBoard in FS mode with a +an Ubuntu 20.04 image and calls m5 exit after the simulation has booted the OS. Usage --- @@ -34,8 +34,7 @@ Usage ``` scons build/RISCV/gem5.opt -./build/RISCV/gem5.opt \ - configs/example/gem5_library/riscvmatched-fs.py +./build/RISCV/gem5.opt configs/example/gem5_library/riscvmatched-fs.py ``` """ From 373b8658f4eb6ffe23412ca63a83cd17d87af0d7 Mon Sep 17 00:00:00 2001 From: "Bobby R. Bruce" Date: Mon, 21 Nov 2022 11:56:23 -0800 Subject: [PATCH 17/45] configs,stdlib: Fix import in riscvmatched-fs.py Change-Id: I2ff4139457d32336f40c6655231064a12c4d8694 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65852 Tested-by: kokoro Maintainer: Bobby Bruce Reviewed-by: Bobby Bruce Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65973 --- configs/example/gem5_library/riscvmatched-fs.py | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/configs/example/gem5_library/riscvmatched-fs.py b/configs/example/gem5_library/riscvmatched-fs.py index 1ed78e81a3..8cf20d9da2 100644 --- a/configs/example/gem5_library/riscvmatched-fs.py +++ b/configs/example/gem5_library/riscvmatched-fs.py @@ -38,9 +38,7 @@ scons build/RISCV/gem5.opt ``` """ -from python.gem5.prebuilt.riscvmatched.riscvmatched_board import ( - RISCVMatchedBoard, -) +from gem5.prebuilt.riscvmatched.riscvmatched_board import RISCVMatchedBoard from gem5.utils.requires import requires from gem5.isas import ISA from gem5.simulate.simulator import Simulator From 793076f2bdfc7e09ed2185e8d7182307f2c534e7 Mon Sep 17 00:00:00 2001 From: "Bobby R. Bruce" Date: Mon, 21 Nov 2022 11:57:40 -0800 Subject: [PATCH 18/45] configs,stdlib,tests: Update riscvmatched-fs.py to-init The "test-gem5-library-example-riscvmatched-fs" test, which runs "configs/example/gem5_library/riscvmatched-fs.py", was running the script in full. This takes a very long time. Given we already have boot tests for RISCV, it's better to just run this configuration to just the end of the Linux boot (significantly faster than a full OS boot). This patch adds this feature to the config script and modifies the test to utilize it. Change-Id: I1e37a26aab5e9a127ebd64590be79fbc16fe53aa Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65853 Reviewed-by: Bobby Bruce Maintainer: Bobby Bruce Tested-by: kokoro Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65974 --- .../example/gem5_library/riscvmatched-fs.py | 26 ++++++++++++++++++- .../test_gem5_library_examples.py | 2 +- 2 files changed, 26 insertions(+), 2 deletions(-) diff --git a/configs/example/gem5_library/riscvmatched-fs.py b/configs/example/gem5_library/riscvmatched-fs.py index 8cf20d9da2..3e84b8c1ea 100644 --- a/configs/example/gem5_library/riscvmatched-fs.py +++ b/configs/example/gem5_library/riscvmatched-fs.py @@ -44,8 +44,23 @@ from gem5.isas import ISA from gem5.simulate.simulator import Simulator from gem5.resources.workload import Workload +import argparse + requires(isa_required=ISA.RISCV) +parser = argparse.ArgumentParser( + description="A script which uses the RISCVMatchedBoard in FS mode." +) + +parser.add_argument( + "-i", + "--to-init", + action="store_true", + help="Exit the simulation after the Linux Kernel boot.", +) + +args = parser.parse_args() + # instantiate the riscv matched board with default parameters board = RISCVMatchedBoard( clk_freq="1.2GHz", @@ -57,7 +72,16 @@ board = RISCVMatchedBoard( # Ubuntu 20.04. Once the system successfully boots it encounters an `m5_exit` # instruction which stops the simulation. When the simulation has ended you may # inspect `m5out/system.pc.com_1.device` to see the stdout. -board.set_workload(Workload("riscv-ubuntu-20.04-boot")) +# +# In the case where the `-i` flag is passed, we add the kernel argument +# `init=/root/exit.sh`. This means the simulation will exit after the Linux +# Kernel has booted. +workload = Workload("riscv-ubuntu-20.04-boot") +kernel_args = board.get_default_kernel_args() +if args.to_init: + kernel_args.append("init=/root/exit.sh") +workload.set_parameter("kernel_args", kernel_args) +board.set_workload(workload) simulator = Simulator(board=board) simulator.run() diff --git a/tests/gem5/gem5_library_example_tests/test_gem5_library_examples.py b/tests/gem5/gem5_library_example_tests/test_gem5_library_examples.py index 28a10b588b..254b15cd4b 100644 --- a/tests/gem5/gem5_library_example_tests/test_gem5_library_examples.py +++ b/tests/gem5/gem5_library_example_tests/test_gem5_library_examples.py @@ -319,7 +319,7 @@ gem5_verify_config( "gem5_library", "riscvmatched-fs.py", ), - config_args=[], + config_args=["--to-init"], valid_isas=(constants.riscv_tag,), valid_hosts=constants.supported_hosts, length=constants.very_long_tag, From 753470e8fa7e3b8e8fd4d3e2ef6b5254a8ea8e8b Mon Sep 17 00:00:00 2001 From: "Bobby R. Bruce" Date: Mon, 21 Nov 2022 12:05:29 -0800 Subject: [PATCH 19/45] tests: Update riscvmatched tests to use ALL/gem5.opt Where possible we are trying to use the ALL/gem5.opt compilation of gem5. This change updates the riscvmatched tests to this. Change-Id: I1c5f1d86cdf5cf29b8964f8a894a3476a7cb290a Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65854 Tested-by: kokoro Reviewed-by: Bobby Bruce Maintainer: Bobby Bruce Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65975 --- .../gem5_library_example_tests/test_gem5_library_examples.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tests/gem5/gem5_library_example_tests/test_gem5_library_examples.py b/tests/gem5/gem5_library_example_tests/test_gem5_library_examples.py index 254b15cd4b..9b5c2c67ff 100644 --- a/tests/gem5/gem5_library_example_tests/test_gem5_library_examples.py +++ b/tests/gem5/gem5_library_example_tests/test_gem5_library_examples.py @@ -303,7 +303,7 @@ gem5_verify_config( "riscvmatched-hello.py", ), config_args=[], - valid_isas=(constants.riscv_tag,), + valid_isas=(constants.all_compiled_tag,), valid_hosts=constants.supported_hosts, length=constants.long_tag, ) @@ -320,7 +320,7 @@ gem5_verify_config( "riscvmatched-fs.py", ), config_args=["--to-init"], - valid_isas=(constants.riscv_tag,), + valid_isas=(constants.all_compiled_tag,), valid_hosts=constants.supported_hosts, length=constants.very_long_tag, ) From d51ce0db94ccf10722ab1135c59758f0e27bf560 Mon Sep 17 00:00:00 2001 From: "Bobby R. Bruce" Date: Mon, 21 Nov 2022 13:25:57 -0800 Subject: [PATCH 20/45] configs: Add missing `_pre_instantiate` call in "run_lupv.py" As of this change: https://gem5-review.googlesource.com/c/public/gem5/+/65051, the `_pre_instantiate` function must be called prior to `m5.instantiate` when using the stdlib without the Simulator module. Change-Id: Id5cec3b643d556b0f742719596abb53533b84cbd Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65871 Reviewed-by: Bobby Bruce Tested-by: kokoro Reviewed-by: Jason Lowe-Power Maintainer: Bobby Bruce Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65976 --- configs/example/lupv/run_lupv.py | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/example/lupv/run_lupv.py b/configs/example/lupv/run_lupv.py index f472f53c69..0056cf8bb4 100644 --- a/configs/example/lupv/run_lupv.py +++ b/configs/example/lupv/run_lupv.py @@ -107,6 +107,7 @@ board.set_kernel_disk_workload( print("Running with ISA: " + processor.get_isa().name) print() root = Root(full_system=True, system=board) +board._pre_instantiate() m5.instantiate() print("Beginning simulation!") From ee9e07474b8b2980727c4219976eaf0696356e78 Mon Sep 17 00:00:00 2001 From: "Bobby R. Bruce" Date: Tue, 22 Nov 2022 14:30:35 -0800 Subject: [PATCH 21/45] tests: Delete build directory before running KVM in nightly The nightly tests failed here: https://jenkins.gem5.org/job/nightly/430/. What seems to have happened is the ALL/gem5.opt us compiled within the Docker container but then, for the KVM tests, there is an attempt to recompile on the host, which causes compilation problems. The safest strategy here is delete the build directory prior to running the KVM tests. In latest versions of our test infrastructure, the KVM tests should be run completely separately (i.e., in different Jenkin's jobs) to avoid this. Change-Id: Id7d18c0504dd324f7a0e5e9a7809463520969dda Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65911 Maintainer: Bobby Bruce Tested-by: kokoro Reviewed-by: Bobby Bruce Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65977 --- tests/nightly.sh | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/tests/nightly.sh b/tests/nightly.sh index a082158e01..ec15f91a78 100755 --- a/tests/nightly.sh +++ b/tests/nightly.sh @@ -89,6 +89,10 @@ docker run -u $UID:$GID --volume "${gem5_root}":"${gem5_root}" -w \ # removes all those part of the 'very-long' (weekly) tests, or for compilation # to '.debug' or '.fast'. We also remove ARM targets as our Jenkins is an X86 # system. Users wishing to run this script elsewhere should be aware of this. +# Note: we delete the build directory here. It was build in the +# "ubuntu-22.04_all-dependencies" docker image which may not be compatible with +# the host environment. +rm -rf "${gem5_root}/build" cd "${gem5_root}/tests" ./main.py run -j${compile_threads} -vv \ --exclude-tags ".*" --include-tags kvm --exclude-tags very\-long \ From ea3f13ff3b52c09a4ef9cfedb1608da7ff55c436 Mon Sep 17 00:00:00 2001 From: Matthew Poremba Date: Wed, 23 Nov 2022 14:20:14 -0800 Subject: [PATCH 22/45] configs: Set CPU vendor to M5 Simulator in apu_se.py Other vendor strings causes, for some reason, bad addresses to be computed when running the GPU model. This change reverts back to M5 Simulator only for apu_se.py. Change-Id: I5992b4e31569f5c0e5e49e523908c8fa0602f845 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66171 Tested-by: kokoro Reviewed-by: Bobby Bruce Maintainer: Bobby Bruce --- configs/example/apu_se.py | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/configs/example/apu_se.py b/configs/example/apu_se.py index b33daa5b39..acf527bdf7 100644 --- a/configs/example/apu_se.py +++ b/configs/example/apu_se.py @@ -740,6 +740,11 @@ if fast_forward: (cpu_list[i], future_cpu_list[i]) for i in range(args.num_cpus) ] +# Other CPU strings cause bad addresses in ROCm. Revert back to M5 Simulator. +for (i, cpu) in enumerate(cpu_list): + for j in range(len(cpu)): + cpu.isa[j].vendor_string = "M5 Simulator" + # Full list of processing cores in the system. cpu_list = cpu_list + [shader] + cp_list From 005049f548dfd260f2057febe000c720779f9c08 Mon Sep 17 00:00:00 2001 From: "Bobby R. Bruce" Date: Wed, 30 Nov 2022 15:02:05 -0800 Subject: [PATCH 23/45] stdlib,python: Allow setting of to tick exits via m5 This commit adds the following functions to the `m5` python module: - setMaxTick(tick) -> None - getMaxTick() -> int - getTicksUntilMax() -> int - scheduleTickExitFromCurrent(tick, exit_string) -> None - scheduleTickExitAbsolute(tick, exit_string) -> None Until this patch the only way to set an exit at a particular tick was via `simulate.run` which would reschedule the maximum tick. This functionality has been explicity exposed via the new `setMaxTick` function. However, as this is only rescheduling the maximum tick, it stops scheduling exits at multiple different ticks. To get around this problem the `scheduleTickExit` functions have been added. These allow a user to schedule multiple exit events. The functions contain a `exit_string` parameter that provides the string the simulator is to return when the specified tick is met. By default this string is "Tick exit reached" which is used by the stdlib Simulator module to declare a new `SCHEDULED_TICK` exit event (Note: this has been deliberatly kept seperate from the `MAX_TICK` exit event. This commit serves as an attempt to decouple these are two concepts). Tests are provided in this patch to ensure these new functions work as intended. Additional notes: - The `simulate` function has been fixed to match the documentation. If the `num_cycles` is -1 then the maximum ticks is set to MaxTicks. Otherwise the max ticks is set to `curTicks() + num_cycles`. The functionality of this function will remain unchanged to the end-user. - Full integration into the Simulator module is not complete as of this patch. Users must us the m5 python module to set these exit events. Change-Id: I6c92b31dd409dc866152224600ea8166cfcba38b Issue-on: https://gem5.atlassian.net/browse/GEM5-1131 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66231 Reviewed-by: Jason Lowe-Power Tested-by: kokoro Maintainer: Jason Lowe-Power Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66331 Reviewed-by: Bobby Bruce Maintainer: Bobby Bruce --- src/python/gem5/simulate/exit_event.py | 3 + src/python/gem5/simulate/simulator.py | 2 + src/python/m5/simulate.py | 59 +++++- src/python/pybind11/event.cc | 4 + src/sim/simulate.cc | 53 +++++- src/sim/simulate.hh | 32 +++- tests/gem5/to_tick/configs/tick-exit.py | 100 ++++++++++ tests/gem5/to_tick/configs/tick-to-max.py | 123 +++++++++++++ .../to_tick/ref/tick-exit-10-20-30-40.txt | 6 + tests/gem5/to_tick/ref/tick-exit-100.txt | 3 + .../ref/tick-to-max-at-execution-100.txt | 4 + ...-to-max-at-execution-and-after-100-200.txt | 4 + .../ref/tick-to-max-before-execution-250.txt | 4 + tests/gem5/to_tick/test_to_tick.py | 174 ++++++++++++++++++ 14 files changed, 561 insertions(+), 10 deletions(-) create mode 100644 tests/gem5/to_tick/configs/tick-exit.py create mode 100644 tests/gem5/to_tick/configs/tick-to-max.py create mode 100644 tests/gem5/to_tick/ref/tick-exit-10-20-30-40.txt create mode 100644 tests/gem5/to_tick/ref/tick-exit-100.txt create mode 100644 tests/gem5/to_tick/ref/tick-to-max-at-execution-100.txt create mode 100644 tests/gem5/to_tick/ref/tick-to-max-at-execution-and-after-100-200.txt create mode 100644 tests/gem5/to_tick/ref/tick-to-max-before-execution-250.txt create mode 100644 tests/gem5/to_tick/test_to_tick.py diff --git a/src/python/gem5/simulate/exit_event.py b/src/python/gem5/simulate/exit_event.py index 089017806b..1e14fdd11a 100644 --- a/src/python/gem5/simulate/exit_event.py +++ b/src/python/gem5/simulate/exit_event.py @@ -42,6 +42,7 @@ class ExitEvent(Enum): SWITCHCPU = "switchcpu" # An exit needed to switch CPU cores. FAIL = "fail" # An exit because the simulation has failed. CHECKPOINT = "checkpoint" # An exit to load a checkpoint. + SCHEDULED_TICK = "scheduled tick exit" MAX_TICK = "max tick" # An exit due to a maximum tick value being met. USER_INTERRUPT = ( # An exit due to a user interrupt (e.g., cntr + c) "user interupt" @@ -75,6 +76,8 @@ class ExitEvent(Enum): return ExitEvent.EXIT elif exit_string == "simulate() limit reached": return ExitEvent.MAX_TICK + elif exit_string == "Tick exit reached": + return ExitEvent.SCHEDULED_TICK elif exit_string == "switchcpu": return ExitEvent.SWITCHCPU elif exit_string == "m5_fail instruction encountered": diff --git a/src/python/gem5/simulate/simulator.py b/src/python/gem5/simulate/simulator.py index 1d0d3ecc66..e27679a996 100644 --- a/src/python/gem5/simulate/simulator.py +++ b/src/python/gem5/simulate/simulator.py @@ -157,6 +157,7 @@ class Simulator: * ExitEvent.WORKEND: exit simulation * ExitEvent.USER_INTERRUPT: exit simulation * ExitEvent.MAX_TICK: exit simulation + * ExitEvent.SCHEDULED_TICK: exit simulation * ExitEvent.SIMPOINT_BEGIN: reset stats * ExitEvent.MAX_INSTS: exit simulation @@ -197,6 +198,7 @@ class Simulator: )(), ExitEvent.USER_INTERRUPT: exit_generator(), ExitEvent.MAX_TICK: exit_generator(), + ExitEvent.SCHEDULED_TICK: exit_generator(), ExitEvent.SIMPOINT_BEGIN: warn_default_decorator( reset_stats_generator, "simpoint begin", diff --git a/src/python/m5/simulate.py b/src/python/m5/simulate.py index a47d4cacd6..744d95f9f6 100644 --- a/src/python/m5/simulate.py +++ b/src/python/m5/simulate.py @@ -54,7 +54,7 @@ from . import params from m5.util.dot_writer import do_dot, do_dvfs_dot from m5.util.dot_writer_ruby import do_ruby_dot -from .util import fatal +from .util import fatal, warn from .util import attrdict # define a MaxTick parameter, unsigned 64 bit @@ -205,6 +205,63 @@ def simulate(*args, **kwargs): return sim_out +def setMaxTick(tick: int) -> None: + """Sets the maximum tick the simulation may run to. When when using the + stdlib simulator module, reaching this max tick triggers a + `ExitEvent.MAX_TICK` exit event. + + :param tick: the maximum tick (absolute, not relative to the current tick). + """ + if tick <= curTick(): + warn("Max tick scheduled for the past. This will not be triggered.") + _m5.event.setMaxTick(tick=tick) + + +def getMaxTick() -> int: + """Returns the current maximum tick.""" + return _m5.event.getMaxTick() + + +def getTicksUntilMax() -> int: + """Returns the current number of ticks until the maximum tick.""" + return getMaxTick() - curTick() + + +def scheduleTickExitFromCurrent( + ticks: int, exit_string: str = "Tick exit reached" +) -> None: + """Schedules a tick exit event from the current tick. I.e., if ticks == 100 + then an exit event will be scheduled at tick `curTick() + 100`. + + The default `exit_string` value is used by the stdlib Simulator module to + declare this exit event as `ExitEvent.SCHEDULED_TICK`. + + :param ticks: The simulation ticks, from `curTick()` to schedule the exit + event. + :param exit_string: The exit string to return when the exit event is + triggered. + """ + scheduleTickExitAbsolute(tick=ticks + curTick(), exit_string=exit_string) + + +def scheduleTickExitAbsolute( + tick: int, exit_string: str = "Tick exit reached" +) -> None: + """Schedules a tick exit event using absolute ticks. I.e., if tick == 100 + then an exit event will be scheduled at tick 100. + + The default `exit_string` value is used by the stdlib Simulator module to + declare this exit event as `ExitEvent.SCHEDULED_TICK`. + + :param tick: The absolute simulation tick to schedule the exit event. + :param exit_string: The exit string to return when the exit event is + triggered. + """ + if tick <= curTick(): + warn("Tick exit scheduled for the past. This will not be triggered.") + _m5.event.scheduleTickExit(tick=tick, exit_string=exit_string) + + def drain(): """Drain the simulator in preparation of a checkpoint or memory mode switch. diff --git a/src/python/pybind11/event.cc b/src/python/pybind11/event.cc index 7a02221611..827768f52f 100644 --- a/src/python/pybind11/event.cc +++ b/src/python/pybind11/event.cc @@ -107,6 +107,10 @@ pybind_init_event(py::module_ &m_native) m.def("simulate", &simulate, py::arg("ticks") = MaxTick); + m.def("setMaxTick", &set_max_tick, py::arg("tick")); + m.def("getMaxTick", &get_max_tick, py::return_value_policy::copy); + m.def("scheduleTickExit", &schedule_tick_exit, py::arg("tick"), + py::arg("exit_string")); m.def("terminateEventQueueThreads", &terminateEventQueueThreads); m.def("exitSimLoop", &exitSimLoop); m.def("getEventQueue", []() { return curEventQueue(); }, diff --git a/src/sim/simulate.cc b/src/sim/simulate.cc index c5d07942ef..4993859036 100644 --- a/src/sim/simulate.cc +++ b/src/sim/simulate.cc @@ -180,16 +180,14 @@ struct DescheduleDeleter }; /** Simulate for num_cycles additional cycles. If num_cycles is -1 - * (the default), do not limit simulation; some other event must - * terminate the loop. Exported to Python. + * (the default), we simulate to MAX_TICKS unless the max ticks has been set + * via the 'set_max_tick' function prior. This function is exported to Python. * @return The SimLoopExitEvent that caused the loop to exit. */ GlobalSimLoopExitEvent * simulate(Tick num_cycles) { std::unique_ptr quantum_event; - const Tick exit_tick = num_cycles < MaxTick - curTick() ? - curTick() + num_cycles : MaxTick; inform("Entering event queue @ %d. Starting simulation...\n", curTick()); @@ -197,11 +195,22 @@ simulate(Tick num_cycles) simulatorThreads.reset(new SimulatorThreads(numMainEventQueues)); if (!simulate_limit_event) { - simulate_limit_event = new GlobalSimLoopExitEvent( - mainEventQueue[0]->getCurTick(), - "simulate() limit reached", 0); + // If the simulate_limit_event is not set, we set it to MaxTick. + set_max_tick(MaxTick); + } + + if (num_cycles != -1) { + // If the user has specified an exit event after X cycles, do so here. + // Note: This will override any prior set max_tick behaviour (such as + // that above when it is set to MAxTick). + const Tick max_tick = num_cycles < MaxTick - curTick() ? + curTick() + num_cycles : MaxTick; + + // This is kept to `set_max_tick` instead of `schedule_tick_exit` to + // preserve backwards functionality. It may be better to deprecate this + // behaviour at some point in favor of `schedule_tick_exit`. + set_max_tick(max_tick); } - simulate_limit_event->reschedule(exit_tick); if (numMainEventQueues > 1) { fatal_if(simQuantum == 0, @@ -231,6 +240,34 @@ simulate(Tick num_cycles) return global_exit_event; } +void set_max_tick(Tick tick) +{ + if (!simulate_limit_event) { + simulate_limit_event = new GlobalSimLoopExitEvent( + mainEventQueue[0]->getCurTick(), + "simulate() limit reached", 0); + } + simulate_limit_event->reschedule(tick); +} + + +Tick get_max_tick() +{ + if (!simulate_limit_event) { + /* If the GlobalSimLoopExitEvent has not been setup, the maximum tick + * is `MaxTick` as declared in "src/base/types.hh". + */ + return MaxTick; + } + + return simulate_limit_event->when(); +} + +void schedule_tick_exit(Tick tick, std::string exit_string) +{ + new GlobalSimLoopExitEvent(tick, exit_string, 0); +} + void terminateEventQueueThreads() { diff --git a/src/sim/simulate.hh b/src/sim/simulate.hh index 5ef499541f..e7c4fa640c 100644 --- a/src/sim/simulate.hh +++ b/src/sim/simulate.hh @@ -45,7 +45,37 @@ namespace gem5 class GlobalSimLoopExitEvent; -GlobalSimLoopExitEvent *simulate(Tick num_cycles = MaxTick); +GlobalSimLoopExitEvent *simulate(Tick num_cycles = -1); + +/** + * @brief Set the maximum tick. + * + * This function will schedule, or reschedule, the maximum tick for the + * simulation. + * + * This will setup the GlobalSimLoopExitEvent if it does not already exist. + * + * @param tick The maximum tick. + */ +void set_max_tick(Tick tick); + +/** + * @brief Get the maximum simulation tick. + * + * + * @returns The maximum simulation tick. + */ +Tick get_max_tick(); + +/** + * @brief Schedule an exit event at a particular tick. + * + * Schedule a tick with a particular exit string. + * + * @param tick The tick at which the simulation loop should exit. + * @param exit_string The exit string explaining the exit. + */ +void schedule_tick_exit(Tick tick, std::string exit_string); /** * Terminate helper threads when running in parallel mode. diff --git a/tests/gem5/to_tick/configs/tick-exit.py b/tests/gem5/to_tick/configs/tick-exit.py new file mode 100644 index 0000000000..9b412cbfb6 --- /dev/null +++ b/tests/gem5/to_tick/configs/tick-exit.py @@ -0,0 +1,100 @@ +# Copyright (c) 2022 The Regents of the University of California +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +""" + +""" + +from gem5.resources.resource import Resource +from gem5.isas import ISA +from gem5.components.memory import SingleChannelDDR3_1600 +from gem5.components.boards.simple_board import SimpleBoard +from gem5.components.cachehierarchies.classic.no_cache import NoCache +from gem5.components.processors.simple_processor import SimpleProcessor +from gem5.components.processors.cpu_types import CPUTypes +from gem5.simulate.simulator import Simulator +from gem5.simulate.exit_event import ExitEvent + +import m5 + +import argparse + +parser = argparse.ArgumentParser() + +parser.add_argument( + "-t", + "--tick-exits", + type=int, + nargs="+", + required=True, + help="Set the tick exits to exit.", +) + +parser.add_argument( + "-r", + "--resource-directory", + type=str, + required=False, + help="The directory in which resources will be downloaded or exist.", +) + +args = parser.parse_args() + +# Setup the system. +motherboard = SimpleBoard( + clk_freq="3GHz", + processor=SimpleProcessor( + cpu_type=CPUTypes.TIMING, + isa=ISA.X86, + num_cores=1, + ), + memory=SingleChannelDDR3_1600(), + cache_hierarchy=NoCache(), +) + +# Set the workload +binary = Resource( + "x86-hello64-static", resource_directory=args.resource_directory +) +motherboard.set_se_binary_workload(binary) + + +def scheduled_tick_generator(): + while True: + print(f"Exiting at: {m5.curTick()}") + yield False + + +# Run the simulation +simulator = Simulator( + board=motherboard, + on_exit_event={ExitEvent.SCHEDULED_TICK: scheduled_tick_generator()}, +) + +for tick in args.tick_exits: + m5.scheduleTickExitFromCurrent(tick) + +simulator.run() diff --git a/tests/gem5/to_tick/configs/tick-to-max.py b/tests/gem5/to_tick/configs/tick-to-max.py new file mode 100644 index 0000000000..2b679df412 --- /dev/null +++ b/tests/gem5/to_tick/configs/tick-to-max.py @@ -0,0 +1,123 @@ +# Copyright (c) 2022 The Regents of the University of California +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +""" +This configuration script is used to test running a simulation to a specified +maximum tick. This script was setup to test setting the number of ticks to +run before, at, or after the running of `simulator.run`. + +**Note:** There can only ever be one MAX_TICK exit event scheduled at any one +time. +""" + +from gem5.resources.resource import Resource +from gem5.isas import ISA +from gem5.components.memory import SingleChannelDDR3_1600 +from gem5.components.boards.simple_board import SimpleBoard +from gem5.components.cachehierarchies.classic.no_cache import NoCache +from gem5.components.processors.simple_processor import SimpleProcessor +from gem5.components.processors.cpu_types import CPUTypes +from gem5.simulate.simulator import Simulator + +import m5 + +import argparse + +parser = argparse.ArgumentParser() + +parser.add_argument( + "-b", + "--set-ticks-before", + type=int, + required=False, + help="Set the number of ticks to run to prior to executing " + "`simulator.run`.", +) + +parser.add_argument( + "-e", + "--set-ticks-at-execution", + type=int, + required=False, + help="Set the number of ticks to run via `simulator.run`.", +) + +parser.add_argument( + "-a", + "--set-ticks-after", + type=int, + required=False, + help="Set the number of ticks to run after `simulator.run` has ceased " + "execution.", +) + +parser.add_argument( + "-r", + "--resource-directory", + type=str, + required=False, + help="The directory in which resources will be downloaded or exist.", +) + +args = parser.parse_args() + +# Setup the system. +motherboard = SimpleBoard( + clk_freq="3GHz", + processor=SimpleProcessor( + cpu_type=CPUTypes.TIMING, + isa=ISA.X86, + num_cores=1, + ), + memory=SingleChannelDDR3_1600(), + cache_hierarchy=NoCache(), +) + +# Set the workload +binary = Resource( + "x86-hello64-static", resource_directory=args.resource_directory +) +motherboard.set_se_binary_workload(binary) + +# Set the max ticks before setting up the simulation, if applicable. +if args.set_ticks_before: + m5.setMaxTick(args.set_ticks_before) + +# Run the simulation +simulator = Simulator(board=motherboard) + +if args.set_ticks_at_execution: + simulator.run(max_ticks=args.set_ticks_at_execution) +else: + simulator.run() + +# Set the max ticks after the simulator run. +if args.set_ticks_after: + m5.setMaxTick(args.set_ticks_after) + +print(f"Current Tick: {m5.curTick()}") +print(f"Current Max Tick: {m5.getMaxTick()}") +print(f"Ticks until max: {m5.getTicksUntilMax()}") diff --git a/tests/gem5/to_tick/ref/tick-exit-10-20-30-40.txt b/tests/gem5/to_tick/ref/tick-exit-10-20-30-40.txt new file mode 100644 index 0000000000..05f8159065 --- /dev/null +++ b/tests/gem5/to_tick/ref/tick-exit-10-20-30-40.txt @@ -0,0 +1,6 @@ +Global frequency set at 1000000000000 ticks per second +Exiting at: 10 +Exiting at: 20 +Exiting at: 30 +Exiting at: 40 +Hello world! diff --git a/tests/gem5/to_tick/ref/tick-exit-100.txt b/tests/gem5/to_tick/ref/tick-exit-100.txt new file mode 100644 index 0000000000..62f9330e13 --- /dev/null +++ b/tests/gem5/to_tick/ref/tick-exit-100.txt @@ -0,0 +1,3 @@ +Global frequency set at 1000000000000 ticks per second +Exiting at: 100 +Hello world! diff --git a/tests/gem5/to_tick/ref/tick-to-max-at-execution-100.txt b/tests/gem5/to_tick/ref/tick-to-max-at-execution-100.txt new file mode 100644 index 0000000000..1507716e42 --- /dev/null +++ b/tests/gem5/to_tick/ref/tick-to-max-at-execution-100.txt @@ -0,0 +1,4 @@ +Global frequency set at 1000000000000 ticks per second +Current Tick: 100 +Current Max Tick: 100 +Ticks until max: 0 diff --git a/tests/gem5/to_tick/ref/tick-to-max-at-execution-and-after-100-200.txt b/tests/gem5/to_tick/ref/tick-to-max-at-execution-and-after-100-200.txt new file mode 100644 index 0000000000..b1cde8ae4c --- /dev/null +++ b/tests/gem5/to_tick/ref/tick-to-max-at-execution-and-after-100-200.txt @@ -0,0 +1,4 @@ +Global frequency set at 1000000000000 ticks per second +Current Tick: 100 +Current Max Tick: 200 +Ticks until max: 100 diff --git a/tests/gem5/to_tick/ref/tick-to-max-before-execution-250.txt b/tests/gem5/to_tick/ref/tick-to-max-before-execution-250.txt new file mode 100644 index 0000000000..b26e9ebee2 --- /dev/null +++ b/tests/gem5/to_tick/ref/tick-to-max-before-execution-250.txt @@ -0,0 +1,4 @@ +Global frequency set at 1000000000000 ticks per second +Current Tick: 250 +Current Max Tick: 250 +Ticks until max: 0 diff --git a/tests/gem5/to_tick/test_to_tick.py b/tests/gem5/to_tick/test_to_tick.py new file mode 100644 index 0000000000..ba5bcbf9b9 --- /dev/null +++ b/tests/gem5/to_tick/test_to_tick.py @@ -0,0 +1,174 @@ +# Copyright (c) 2022 The Regents of the University of California +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +from testlib import * + +if config.bin_path: + resource_path = config.bin_path +else: + resource_path = joinpath(absdirpath(__file__), "..", "resources") + +# This test sets the tick to max tick via the `simulator.run` function. This is +# set to 100. Therefore, at the end of the execution the expected current tick +# should be 100, with the max tick still 100. The number of expected ticks to +# max is therefore 0. +gem5_verify_config( + name="test-to-max-tick-at-execution-100", + verifiers=[ + verifier.MatchStdoutNoPerf( + joinpath(getcwd(), "ref", "tick-to-max-at-execution-100.txt") + ) + ], + fixtures=(), + config=joinpath( + config.base_dir, + "tests", + "gem5", + "to_tick", + "configs", + "tick-to-max.py", + ), + config_args=[ + "--resource-directory", + resource_path, + "--set-ticks-at-execution", + "100", + ], + valid_isas=(constants.all_compiled_tag,), + valid_hosts=constants.supported_hosts, + length=constants.quick_tag, +) + +# This test sets the max tick via the `simulator.run` function at tick 100. +# The `m5.setMaxTick` function is then called after, passing the value 200 . +# This means at the end of execution the current tick is 100, and the max tick +# is 200. The number of expected ticks to max is therefore 100. +gem5_verify_config( + name="test-to-max-tick-at-execution-and-after-100-200", + verifiers=[ + verifier.MatchStdoutNoPerf( + joinpath( + getcwd(), + "ref", + "tick-to-max-at-execution-and-after-100-200.txt", + ) + ) + ], + fixtures=(), + config=joinpath( + config.base_dir, + "tests", + "gem5", + "to_tick", + "configs", + "tick-to-max.py", + ), + config_args=[ + "--resource-directory", + resource_path, + "--set-ticks-at-execution", + "100", + "--set-ticks-after", + "200", + ], + valid_isas=(constants.all_compiled_tag,), + valid_hosts=constants.supported_hosts, + length=constants.quick_tag, +) + +# This test sets the max tick to 250 via the `m5.setMaxTick` prior to running +# `simulator.run`. This means at the end of execution the current tick is 250 +# and the max tick is 250. The expected number of ticks to max is therefore 0. +gem5_verify_config( + name="test-to-max-tick-before-execution-250", + verifiers=[ + verifier.MatchStdoutNoPerf( + joinpath(getcwd(), "ref", "tick-to-max-before-execution-250.txt") + ) + ], + fixtures=(), + config=joinpath( + config.base_dir, + "tests", + "gem5", + "to_tick", + "configs", + "tick-to-max.py", + ), + config_args=[ + "--resource-directory", + resource_path, + "--set-ticks-before", + "250", + ], + valid_isas=(constants.all_compiled_tag,), + valid_hosts=constants.supported_hosts, + length=constants.quick_tag, +) + +# Tests the scheduling of a tick exit event at tick 100. +gem5_verify_config( + name="test-to-tick-exit-100", + verifiers=[ + verifier.MatchStdoutNoPerf( + joinpath(getcwd(), "ref", "tick-exit-100.txt") + ) + ], + fixtures=(), + config=joinpath( + config.base_dir, "tests", "gem5", "to_tick", "configs", "tick-exit.py" + ), + config_args=["--resource-directory", resource_path, "--tick-exits", "100"], + valid_isas=(constants.all_compiled_tag,), + valid_hosts=constants.supported_hosts, + length=constants.quick_tag, +) + +# Tests the scheduling of a tick exit event at tick 10, 20, 30, and 40. +gem5_verify_config( + name="test-to-tick-exit-10-20-30-40", + verifiers=[ + verifier.MatchStdoutNoPerf( + joinpath(getcwd(), "ref", "tick-exit-10-20-30-40.txt") + ) + ], + fixtures=(), + config=joinpath( + config.base_dir, "tests", "gem5", "to_tick", "configs", "tick-exit.py" + ), + config_args=[ + "--resource-directory", + resource_path, + "--tick-exits", + "10", + "20", + "30", + "40", + ], + valid_isas=(constants.all_compiled_tag,), + valid_hosts=constants.supported_hosts, + length=constants.quick_tag, +) From 6f3f6c16f3bdd5333eec157cd6db88199deab5fc Mon Sep 17 00:00:00 2001 From: Melissa Jost Date: Tue, 18 Oct 2022 16:04:18 -0700 Subject: [PATCH 24/45] stdlib, configs: Updating configs/example/gem5_library This commit updates all of the older tests in this directory to use the Simulator to run instead of m5.simulate() Change-Id: I2a81d5c2f27c89e8c03abb0203ca3e58a6688672 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64791 Reviewed-by: Bobby Bruce Tested-by: kokoro Maintainer: Bobby Bruce Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66332 --- .../gem5_library/x86-gapbs-benchmarks.py | 101 +++--------- .../gem5_library/x86-npb-benchmarks.py | 145 ++++++------------ .../gem5_library/x86-parsec-benchmarks.py | 110 +++---------- .../x86-spec-cpu2006-benchmarks.py | 117 +++----------- .../x86-spec-cpu2017-benchmarks.py | 109 +++---------- 5 files changed, 144 insertions(+), 438 deletions(-) diff --git a/configs/example/gem5_library/x86-gapbs-benchmarks.py b/configs/example/gem5_library/x86-gapbs-benchmarks.py index bdc0d9427d..638d34b599 100644 --- a/configs/example/gem5_library/x86-gapbs-benchmarks.py +++ b/configs/example/gem5_library/x86-gapbs-benchmarks.py @@ -64,8 +64,8 @@ from gem5.components.processors.cpu_types import CPUTypes from gem5.isas import ISA from gem5.coherence_protocol import CoherenceProtocol from gem5.resources.resource import Resource - -from m5.stats.gem5stats import get_simstat +from gem5.simulate.simulator import Simulator +from gem5.simulate.exit_event import ExitEvent requires( isa_required=ISA.X86, @@ -210,14 +210,26 @@ board.set_kernel_disk_workload( readfile_contents=command, ) -root = Root(full_system=True, system=board) -# sim_quantum must be set when KVM cores are used. +def handle_exit(): + print("Done booting Linux") + print("Resetting stats at the start of ROI!") + m5.stats.reset() + global start_tick + start_tick = m5.curTick() + processor.switch() + yield False # E.g., continue the simulation. + print("Dump stats at the end of the ROI!") + m5.stats.dump() + yield True # Stop the simulation. We're done. -root.sim_quantum = int(1e9) -board._pre_instantiate() -m5.instantiate() +simulator = Simulator( + board=board, + on_exit_event={ + ExitEvent.EXIT: handle_exit(), + }, +) # We maintain the wall clock time. @@ -232,74 +244,8 @@ print("Using KVM cpu") # the first ROI annotation in details. The X86Board currently does not support # `work items started count reached`. -exit_event = m5.simulate() - -# The first exit_event ends with a `workbegin` cause. This means that the -# system started successfully and the execution on the program started. The -# ROI begin is encountered. - -if exit_event.getCause() == "workbegin": - - print("Done booting Linux") - print("Resetting stats at the start of ROI!") - - m5.stats.reset() - start_tick = m5.curTick() - - # We have completed up to this step using KVM cpu. Now we switch to timing - # cpu for detailed simulation. - - processor.switch() -else: - print("Unexpected termination of simulation before ROI was reached!") - print( - "Exiting @ tick {} because {}.".format( - m5.curTick(), exit_event.getCause() - ) - ) - exit(-1) - -# The next exit_event is to simulate the ROI. It should be exited with a cause -# marked by `workend`. This implies that the first annotation is successfully -# completed. - -exit_event = m5.simulate() - -# Reached the end of first ROI. -# We dump the stats here. - -# We exepect that ROI ends with `workend`. Otherwise the simulation ended -# unexpectedly. -if exit_event.getCause() == "workend": - print("Dump stats at the end of the ROI!") - - m5.stats.dump() - end_tick = m5.curTick() -else: - print("Unexpected termination of simulation while ROI was being executed!") - print( - "Exiting @ tick {} because {}.".format( - m5.curTick(), exit_event.getCause() - ) - ) - exit(-1) - -# We get simInsts using get_simstat and output it in the final print statement. - -gem5stats = get_simstat(root) - -# We get the number of committed instructions from the timing cores. We then -# sum and print them at the end. - -roi_insts = float( - gem5stats.to_json()["system"]["processor"]["switch0"]["core"][ - "exec_context.thread_0" - ]["numInsts"]["value"] -) + float( - gem5stats.to_json()["system"]["processor"]["switch1"]["core"][ - "exec_context.thread_0" - ]["numInsts"]["value"] -) +simulator.run() +end_tick = m5.curTick() # Since we simulated the ROI in details, therefore, simulation is over at this # point. @@ -313,8 +259,9 @@ print() print("Performance statistics:") print("Simulated time in ROI: %.2fs" % ((end_tick - start_tick) / 1e12)) -print("Instructions executed in ROI: %d" % ((roi_insts))) -print("Ran a total of", m5.curTick() / 1e12, "simulated seconds") +print( + "Ran a total of", simulator.get_current_tick() / 1e12, "simulated seconds" +) print( "Total wallclock time: %.2fs, %.2f min" % (time.time() - globalStart, (time.time() - globalStart) / 60) diff --git a/configs/example/gem5_library/x86-npb-benchmarks.py b/configs/example/gem5_library/x86-npb-benchmarks.py index 385760c7a7..2cb314303f 100644 --- a/configs/example/gem5_library/x86-npb-benchmarks.py +++ b/configs/example/gem5_library/x86-npb-benchmarks.py @@ -61,6 +61,8 @@ from gem5.components.processors.cpu_types import CPUTypes from gem5.isas import ISA from gem5.coherence_protocol import CoherenceProtocol from gem5.resources.resource import Resource +from gem5.simulate.simulator import Simulator +from gem5.simulate.simulator import ExitEvent from m5.stats.gem5stats import get_simstat from m5.util import warn @@ -209,17 +211,47 @@ board.set_kernel_disk_workload( readfile_contents=command, ) -# We need this for long running processes. -m5.disableAllListeners() +# The first exit_event ends with a `workbegin` cause. This means that the +# system started successfully and the execution on the program started. +def handle_workbegin(): + print("Done booting Linux") + print("Resetting stats at the start of ROI!") -root = Root(full_system=True, system=board) + m5.stats.reset() -# sim_quantum must be set when KVM cores are used. + # We have completed up to this step using KVM cpu. Now we switch to timing + # cpu for detailed simulation. -root.sim_quantum = int(1e9) + # # Next, we need to check if the user passed a value for --ticks. If yes, + # then we limit out execution to this number of ticks during the ROI. + # Otherwise, we simulate until the ROI ends. + processor.switch() + if args.ticks: + # schedule an exit event for this amount of ticks in the future. + # The simulation will then continue. + m5.scheduleTickExitFromCurrent(args.ticks) + yield False -board._pre_instantiate() -m5.instantiate() + +# The next exit_event is to simulate the ROI. It should be exited with a cause +# marked by `workend`. + +# We exepect that ROI ends with `workend` or `simulate() limit reached`. +# Otherwise the simulation ended unexpectedly. +def handle_workend(): + print("Dump stats at the end of the ROI!") + + m5.stats.dump() + yield False + + +simulator = Simulator( + board=board, + on_exit_event={ + ExitEvent.WORKBEGIN: handle_workbegin(), + ExitEvent.WORKEND: handle_workend(), + }, +) # We maintain the wall clock time. @@ -229,96 +261,12 @@ print("Running the simulation") print("Using KVM cpu") # We start the simulation. - -exit_event = m5.simulate() - -# The first exit_event ends with a `workbegin` cause. This means that the -# system started successfully and the execution on the program started. - -if exit_event.getCause() == "workbegin": - - print("Done booting Linux") - print("Resetting stats at the start of ROI!") - - m5.stats.reset() - start_tick = m5.curTick() - - # We have completed up to this step using KVM cpu. Now we switch to timing - # cpu for detailed simulation. - - processor.switch() -else: - # `workbegin` call was never encountered. - - print("Unexpected termination of simulation before ROI was reached!") - print( - "Exiting @ tick {} because {}.".format( - m5.curTick(), exit_event.getCause() - ) - ) - exit(-1) - -# The next exit_event is to simulate the ROI. It should be exited with a cause -# marked by `workend`. - -# Next, we need to check if the user passed a value for --ticks. If yes, -# then we limit out execution to this number of ticks during the ROI. -# Otherwise, we simulate until the ROI ends. -if args.ticks: - exit_event = m5.simulate(args.ticks) -else: - exit_event = m5.simulate() - - -# Reached the end of ROI. -# We dump the stats here. - -# We exepect that ROI ends with `workend` or `simulate() limit reached`. -# Otherwise the simulation ended unexpectedly. -if exit_event.getCause() == "workend": - print("Dump stats at the end of the ROI!") - - m5.stats.dump() - end_tick = m5.curTick() -elif ( - exit_event.getCause() == "simulate() limit reached" - and args.ticks is not None -): - print("Dump stats at the end of {} ticks in the ROI".format(args.ticks)) - - m5.stats.dump() - end_tick = m5.curTick() -else: - print("Unexpected termination of simulation while ROI was being executed!") - print( - "Exiting @ tick {} because {}.".format( - m5.curTick(), exit_event.getCause() - ) - ) - exit(-1) +simulator.run() # We need to note that the benchmark is not executed completely till this # point, but, the ROI has. We collect the essential statistics here before # resuming the simulation again. -# We get simInsts using get_simstat and output it in the final -# print statement. - -gem5stats = get_simstat(root) - -# We get the number of committed instructions from the timing -# cores. We then sum and print them at the end. - -roi_insts = float( - gem5stats.to_json()["system"]["processor"]["switch0"]["core"][ - "exec_context.thread_0" - ]["numInsts"]["value"] -) + float( - gem5stats.to_json()["system"]["processor"]["switch1"]["core"][ - "exec_context.thread_0" - ]["numInsts"]["value"] -) - # Simulation is over at this point. We acknowledge that all the simulation # events were successful. print("All simulation events were successful.") @@ -328,9 +276,16 @@ print("Done with the simulation") print() print("Performance statistics:") -print("Simulated time in ROI: %.2fs" % ((end_tick - start_tick) / 1e12)) -print("Instructions executed in ROI: %d" % ((roi_insts))) -print("Ran a total of", m5.curTick() / 1e12, "simulated seconds") +# manually calculate ROI time if ticks arg is used in case the +# entire ROI wasn't simulated +if args.ticks: + print(f"Simulated time in ROI (to tick): {args.ticks/ 1e12}s") +else: + print(f"Simulated time in ROI: {simulator.get_roi_ticks()[0] / 1e12}s") + +print( + f"Ran a total of {simulator.get_current_tick() / 1e12} simulated seconds" +) print( "Total wallclock time: %.2fs, %.2f min" % (time.time() - globalStart, (time.time() - globalStart) / 60) diff --git a/configs/example/gem5_library/x86-parsec-benchmarks.py b/configs/example/gem5_library/x86-parsec-benchmarks.py index 82183802c7..190c0a0980 100644 --- a/configs/example/gem5_library/x86-parsec-benchmarks.py +++ b/configs/example/gem5_library/x86-parsec-benchmarks.py @@ -60,8 +60,8 @@ from gem5.components.processors.cpu_types import CPUTypes from gem5.isas import ISA from gem5.coherence_protocol import CoherenceProtocol from gem5.resources.resource import Resource - -from m5.stats.gem5stats import get_simstat +from gem5.simulate.simulator import Simulator +from gem5.simulate.exit_event import ExitEvent # We check for the required gem5 build. @@ -195,17 +195,28 @@ board.set_kernel_disk_workload( readfile_contents=command, ) -# We need this for long running processes. -m5.disableAllListeners() +# functions to handle different exit events during the simuation +def handle_workbegin(): + print("Done booting Linux") + print("Resetting stats at the start of ROI!") + m5.stats.reset() + processor.switch() + yield False -root = Root(full_system=True, system=board) -# sim_quantum must be set if KVM cores are used. +def handle_workend(): + print("Dump stats at the end of the ROI!") + m5.stats.dump() + yield True -root.sim_quantum = int(1e9) -board._pre_instantiate() -m5.instantiate() +simulator = Simulator( + board=board, + on_exit_event={ + ExitEvent.WORKBEGIN: handle_workbegin(), + ExitEvent.WORKEND: handle_workend(), + }, +) # We maintain the wall clock time. @@ -214,83 +225,11 @@ globalStart = time.time() print("Running the simulation") print("Using KVM cpu") -start_tick = m5.curTick() -end_tick = m5.curTick() m5.stats.reset() # We start the simulation +simulator.run() -exit_event = m5.simulate() - -# The first exit_event ends with a `workbegin` cause. This means that the -# system booted successfully and the execution on the program started. - -if exit_event.getCause() == "workbegin": - - print("Done booting Linux") - print("Resetting stats at the start of ROI!") - - m5.stats.reset() - start_tick = m5.curTick() - - # We have completed up to this step using KVM cpu. Now we switch to timing - # cpu for detailed simulation. - - processor.switch() -else: - # `workbegin` call was never encountered. - - print("Unexpected termination of simulation before ROI was reached!") - print( - "Exiting @ tick {} because {}.".format( - m5.curTick(), exit_event.getCause() - ) - ) - exit(-1) - -# The next exit_event is to simulate the ROI. It should be exited with a cause -# marked by `workend`. - -exit_event = m5.simulate() - -# Reached the end of ROI. -# We dump the stats here. - -# We exepect that ROI ends with `workend`. Otherwise the simulation ended -# unexpectedly. -if exit_event.getCause() == "workend": - print("Dump stats at the end of the ROI!") - - m5.stats.dump() - end_tick = m5.curTick() -else: - print("Unexpected termination of simulation while ROI was being executed!") - print( - "Exiting @ tick {} because {}.".format( - m5.curTick(), exit_event.getCause() - ) - ) - exit(-1) - -# ROI has ended here, and we get `simInsts` using get_simstat and print it in -# the final print statement. - -gem5stats = get_simstat(root) - -# We get the number of committed instructions from the timing -# cores. We then sum and print them at the end. -roi_insts = float( - gem5stats.to_json()["system"]["processor"]["switch0"]["core"][ - "exec_context.thread_0" - ]["numInsts"]["value"] -) + float( - gem5stats.to_json()["system"]["processor"]["switch1"]["core"][ - "exec_context.thread_0" - ]["numInsts"]["value"] -) - -# Simulation is over at this point. We acknowledge that all the simulation -# events were successful. print("All simulation events were successful.") # We print the final simulation statistics. @@ -299,9 +238,10 @@ print("Done with the simulation") print() print("Performance statistics:") -print("Simulated time in ROI: %.2fs" % ((end_tick - start_tick) / 1e12)) -print("Instructions executed in ROI: %d" % ((roi_insts))) -print("Ran a total of", m5.curTick() / 1e12, "simulated seconds") +print("Simulated time in ROI: " + ((str(simulator.get_roi_ticks()[0])))) +print( + "Ran a total of", simulator.get_current_tick() / 1e12, "simulated seconds" +) print( "Total wallclock time: %.2fs, %.2f min" % (time.time() - globalStart, (time.time() - globalStart) / 60) diff --git a/configs/example/gem5_library/x86-spec-cpu2006-benchmarks.py b/configs/example/gem5_library/x86-spec-cpu2006-benchmarks.py index d656e61145..8f39f49e2e 100644 --- a/configs/example/gem5_library/x86-spec-cpu2006-benchmarks.py +++ b/configs/example/gem5_library/x86-spec-cpu2006-benchmarks.py @@ -66,6 +66,8 @@ from gem5.components.processors.cpu_types import CPUTypes from gem5.isas import ISA from gem5.coherence_protocol import CoherenceProtocol from gem5.resources.resource import Resource, CustomDiskImageResource +from gem5.simulate.simulator import Simulator +from gem5.simulate.exit_event import ExitEvent from m5.stats.gem5stats import get_simstat from m5.util import warn @@ -265,17 +267,23 @@ board.set_kernel_disk_workload( readfile_contents=command, ) -# We need this for long running processes. -m5.disableAllListeners() -root = Root(full_system=True, system=board) +def handle_exit(): + print("Done bootling Linux") + print("Resetting stats at the start of ROI!") + m5.stats.reset() + yield False # E.g., continue the simulation. + print("Dump stats at the end of the ROI!") + m5.stats.dump() + yield True # Stop the simulation. We're done. -# sim_quantum must be set when KVM cores are used. -root.sim_quantum = int(1e9) - -board._pre_instantiate() -m5.instantiate() +simulator = Simulator( + board=board, + on_exit_event={ + ExitEvent.EXIT: handle_exit(), + }, +) # We maintain the wall clock time. @@ -284,92 +292,10 @@ globalStart = time.time() print("Running the simulation") print("Using KVM cpu") -start_tick = m5.curTick() -end_tick = m5.curTick() m5.stats.reset() -exit_event = m5.simulate() - -if exit_event.getCause() == "m5_exit instruction encountered": - # We have completed booting the OS using KVM cpu - # Reached the start of ROI - - print("Done booting Linux") - print("Resetting stats at the start of ROI!") - - m5.stats.reset() - start_tick = m5.curTick() - - # We switch to timing cpu for detailed simulation. - - processor.switch() -else: - # `m5_exit instruction encountered` was never reached - - print("Unexpected termination of simulation before ROI was reached!") - print( - "Exiting @ tick {} because {}.".format( - m5.curTick(), exit_event.getCause() - ) - ) - exit(-1) - -# Simulate the ROI -exit_event = m5.simulate() - -# Reached the end of ROI -gem5stats = get_simstat(root) - -# We get the number of committed instructions from the timing -# cores. We then sum and print them at the end. - -roi_insts = float( - json.loads(gem5stats.dumps())["system"]["processor"]["cores2"]["core"][ - "exec_context.thread_0" - ]["numInsts"]["value"] -) + float( - json.loads(gem5stats.dumps())["system"]["processor"]["cores3"]["core"][ - "exec_context.thread_0" - ]["numInsts"]["value"] -) - -if exit_event.getCause() == "m5_exit instruction encountered": - print("Dump stats at the end of the ROI!") - m5.stats.dump() - end_tick = m5.curTick() - m5.stats.reset() - -else: - # `m5_exit instruction encountered` was never reached - - print("Unexpected termination of simulation while ROI was being executed!") - print( - "Exiting @ tick {} because {}.".format( - m5.curTick(), exit_event.getCause() - ) - ) - exit(-1) - -# We need to copy back the contents of the `speclogs' directory to -# m5.options.outdir - -exit_event = m5.simulate() - -if exit_event.getCause() == "m5_exit instruction encountered": - print("Output logs copied!") - -else: - print("Unexpected termination of simulation while copying speclogs!") - print( - "Exiting @ tick {} because {}.".format( - m5.curTick(), exit_event.getCause() - ) - ) - exit(-1) - -m5.stats.dump() -end_tick = m5.curTick() -m5.stats.reset() +# We start the simulation +simulator.run() # Simulation is over at this point. We acknowledge that all the simulation # events were successful. @@ -378,9 +304,10 @@ print("All simulation events were successful.") print("Performance statistics:") -print("Simulated time: %.2fs" % ((end_tick - start_tick) / 1e12)) -print("Instructions executed: %d" % ((roi_insts))) -print("Ran a total of", m5.curTick() / 1e12, "simulated seconds") +print("Simulated time: " + ((str(simulator.get_roi_ticks()[0])))) +print( + "Ran a total of", simulator.get_current_tick() / 1e12, "simulated seconds" +) print( "Total wallclock time: %.2fs, %.2f min" % (time.time() - globalStart, (time.time() - globalStart) / 60) diff --git a/configs/example/gem5_library/x86-spec-cpu2017-benchmarks.py b/configs/example/gem5_library/x86-spec-cpu2017-benchmarks.py index 2bc948aea1..c4af7f5dd9 100644 --- a/configs/example/gem5_library/x86-spec-cpu2017-benchmarks.py +++ b/configs/example/gem5_library/x86-spec-cpu2017-benchmarks.py @@ -64,6 +64,8 @@ from gem5.components.processors.cpu_types import CPUTypes from gem5.isas import ISA from gem5.coherence_protocol import CoherenceProtocol from gem5.resources.resource import Resource, CustomDiskImageResource +from gem5.simulate.simulator import Simulator +from gem5.simulate.exit_event import ExitEvent from m5.stats.gem5stats import get_simstat from m5.util import warn @@ -281,17 +283,23 @@ board.set_kernel_disk_workload( readfile_contents=command, ) -# We need this for long running processes. -m5.disableAllListeners() -root = Root(full_system=True, system=board) +def handle_exit(): + print("Done bootling Linux") + print("Resetting stats at the start of ROI!") + m5.stats.reset() + yield False # E.g., continue the simulation. + print("Dump stats at the end of the ROI!") + m5.stats.dump() + yield True # Stop the simulation. We're done. -# sim_quantum must be set when KVM cores are used. -root.sim_quantum = int(1e9) - -board._pre_instantiate() -m5.instantiate() +simulator = Simulator( + board=board, + on_exit_event={ + ExitEvent.EXIT: handle_exit(), + }, +) # We maintain the wall clock time. @@ -300,92 +308,21 @@ globalStart = time.time() print("Running the simulation") print("Using KVM cpu") -start_tick = m5.curTick() -end_tick = m5.curTick() m5.stats.reset() -exit_event = m5.simulate() +# We start the simulation +simulator.run() -if exit_event.getCause() == "m5_exit instruction encountered": - # We have completed booting the OS using KVM cpu - # Reached the start of ROI - - print("Done booting Linux") - print("Resetting stats at the start of ROI!") - - m5.stats.reset() - start_tick = m5.curTick() - - # We switch to timing cpu for detailed simulation. - - processor.switch() -else: - print("Unexpected termination of simulation before ROI was reached!") - print( - "Exiting @ tick {} because {}.".format( - m5.curTick(), exit_event.getCause() - ) - ) - exit(-1) - -# Simulate the ROI -exit_event = m5.simulate() - -# Reached the end of ROI -gem5stats = get_simstat(root) - -# We get the number of committed instructions from the timing -# cores. We then sum and print them at the end. - -roi_insts = float( - json.loads(gem5stats.dumps())["system"]["processor"]["cores2"]["core"][ - "exec_context.thread_0" - ]["numInsts"]["value"] -) + float( - json.loads(gem5stats.dumps())["system"]["processor"]["cores3"]["core"][ - "exec_context.thread_0" - ]["numInsts"]["value"] -) - -if exit_event.getCause() == "m5_exit instruction encountered": - print("Dump stats at the end of the ROI!") - m5.stats.dump() - end_tick = m5.curTick() - m5.stats.reset() - -else: - print("Unexpected termination of simulation while ROI was being executed!") - print( - "Exiting @ tick {} because {}.".format( - m5.curTick(), exit_event.getCause() - ) - ) - exit(-1) - -# We need to copy back the contents of the `speclogs' directory to -# m5.options.outdir - -exit_event = m5.simulate() - -if exit_event.getCause() == "m5_exit instruction encountered": - print("Output logs copied!") - -else: - print("Unexpected termination of simulation while copying speclogs!") - print( - "Exiting @ tick {} because {}.".format( - m5.curTick(), exit_event.getCause() - ) - ) - exit(-1) +# We print the final simulation statistics. print("Done with the simulation") print() print("Performance statistics:") -print("Simulated time in ROI: %.2fs" % ((end_tick - start_tick) / 1e12)) -print("Instructions executed in ROI: %d" % ((roi_insts))) -print("Ran a total of", m5.curTick() / 1e12, "simulated seconds") +print("Simulated time in ROI: " + ((str(simulator.get_roi_ticks()[0])))) +print( + "Ran a total of", simulator.get_current_tick() / 1e12, "simulated seconds" +) print( "Total wallclock time: %.2fs, %.2f min" % (time.time() - globalStart, (time.time() - globalStart) / 60) From 23a406e8111badb601890dffc7edc93dbed68d56 Mon Sep 17 00:00:00 2001 From: Giacomo Travaglini Date: Wed, 23 Nov 2022 08:35:50 +0000 Subject: [PATCH 25/45] arch-arm: Setup TC/ISA at construction time 2nd attempt This partly reverts commit ec75787aef56665e893d70293bf3a0f93c33bb6a by fixing the original problem noted by Bobby (long regressions): setupThreadContext has to be implemented otherswise the GICv3 cpu interface will end up holding old references when switching TC/ISAs. This new implementation is still setting up the cpu interface reference in the ISA only when it is required, but it is storing the TC/ISA reference within the interface every time the ISA::setupThreadContext gets called. Change-Id: I2f54f95761d63655162c253e887b872f3718c764 Signed-off-by: Giacomo Travaglini Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66291 Maintainer: Bobby Bruce Maintainer: Andreas Sandberg Reviewed-by: Andreas Sandberg Tested-by: kokoro Reviewed-by: Bobby Bruce --- src/arch/arm/isa.cc | 33 ++++++++++++++++++++--------- src/arch/arm/isa.hh | 1 + src/dev/arm/gic_v3.cc | 2 +- src/dev/arm/gic_v3_cpu_interface.cc | 8 +++++-- src/dev/arm/gic_v3_cpu_interface.hh | 6 +++--- 5 files changed, 34 insertions(+), 16 deletions(-) diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index a30fd94596..543e0eba7b 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -524,15 +524,10 @@ ISA::setupThreadContext() selfDebug->init(tc); - Gicv3 *gicv3 = dynamic_cast(system->getGIC()); - if (!gicv3) - return; - - if (!gicv3CpuInterface) - gicv3CpuInterface.reset(gicv3->getCPUInterface(tc->contextId())); - - gicv3CpuInterface->setISA(this); - gicv3CpuInterface->setThreadContext(tc); + if (auto gicv3_ifc = getGICv3CPUInterface(tc); gicv3_ifc) { + gicv3_ifc->setISA(this); + gicv3_ifc->setThreadContext(tc); + } } void @@ -2008,10 +2003,28 @@ ISA::getGenericTimer() BaseISADevice & ISA::getGICv3CPUInterface() { - panic_if(!gicv3CpuInterface, "GICV3 cpu interface is not registered!"); + if (gicv3CpuInterface) + return *gicv3CpuInterface.get(); + + auto gicv3_ifc = getGICv3CPUInterface(tc); + panic_if(!gicv3_ifc, "The system does not have a GICv3 irq controller\n"); + gicv3CpuInterface.reset(gicv3_ifc); + return *gicv3CpuInterface.get(); } +BaseISADevice* +ISA::getGICv3CPUInterface(ThreadContext *tc) +{ + assert(system); + Gicv3 *gicv3 = dynamic_cast(system->getGIC()); + if (gicv3) { + return gicv3->getCPUInterface(tc->contextId()); + } else { + return nullptr; + } +} + bool ISA::inSecureState() const { diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh index 1f7a7561a7..9e1afa714b 100644 --- a/src/arch/arm/isa.hh +++ b/src/arch/arm/isa.hh @@ -116,6 +116,7 @@ namespace ArmISA BaseISADevice &getGenericTimer(); BaseISADevice &getGICv3CPUInterface(); + BaseISADevice *getGICv3CPUInterface(ThreadContext *tc); RegVal miscRegs[NUM_MISCREGS]; const RegId *intRegMap; diff --git a/src/dev/arm/gic_v3.cc b/src/dev/arm/gic_v3.cc index dde3818b07..e14d1f2bef 100644 --- a/src/dev/arm/gic_v3.cc +++ b/src/dev/arm/gic_v3.cc @@ -147,7 +147,7 @@ Gicv3::init() for (int i = 0; i < threads; i++) { redistributors[i] = new Gicv3Redistributor(this, i); - cpuInterfaces[i] = new Gicv3CPUInterface(this, i); + cpuInterfaces[i] = new Gicv3CPUInterface(this, sys->threads[i]); } distRange = RangeSize(params().dist_addr, diff --git a/src/dev/arm/gic_v3_cpu_interface.cc b/src/dev/arm/gic_v3_cpu_interface.cc index 0e1dbaa04b..28a173943d 100644 --- a/src/dev/arm/gic_v3_cpu_interface.cc +++ b/src/dev/arm/gic_v3_cpu_interface.cc @@ -55,15 +55,19 @@ using namespace ArmISA; const uint8_t Gicv3CPUInterface::GIC_MIN_BPR; const uint8_t Gicv3CPUInterface::GIC_MIN_BPR_NS; -Gicv3CPUInterface::Gicv3CPUInterface(Gicv3 * gic, uint32_t cpu_id) +Gicv3CPUInterface::Gicv3CPUInterface(Gicv3 * gic, ThreadContext *_tc) : BaseISADevice(), gic(gic), redistributor(nullptr), distributor(nullptr), - cpuId(cpu_id) + tc(_tc), + maintenanceInterrupt(gic->params().maint_int->get(tc)), + cpuId(tc->contextId()) { hppi.prio = 0xff; hppi.intid = Gicv3::INTID_SPURIOUS; + + setISA(static_cast(tc->getIsaPtr())); } void diff --git a/src/dev/arm/gic_v3_cpu_interface.hh b/src/dev/arm/gic_v3_cpu_interface.hh index e860373fb5..ff476bc3c6 100644 --- a/src/dev/arm/gic_v3_cpu_interface.hh +++ b/src/dev/arm/gic_v3_cpu_interface.hh @@ -68,10 +68,10 @@ class Gicv3CPUInterface : public ArmISA::BaseISADevice, public Serializable Gicv3 * gic; Gicv3Redistributor * redistributor; Gicv3Distributor * distributor; - uint32_t cpuId; - ArmInterruptPin *maintenanceInterrupt; ThreadContext *tc; + ArmInterruptPin *maintenanceInterrupt; + uint32_t cpuId; BitUnion64(ICC_CTLR_EL1) Bitfield<63, 20> res0_3; @@ -359,7 +359,7 @@ class Gicv3CPUInterface : public ArmISA::BaseISADevice, public Serializable void setBankedMiscReg(ArmISA::MiscRegIndex misc_reg, RegVal val) const; public: - Gicv3CPUInterface(Gicv3 * gic, uint32_t cpu_id); + Gicv3CPUInterface(Gicv3 * gic, ThreadContext *tc); void init(); From 7dd61c865975862b099e1af5e867083ac9307d9b Mon Sep 17 00:00:00 2001 From: "Bobby R. Bruce" Date: Mon, 21 Nov 2022 13:48:29 -0800 Subject: [PATCH 26/45] scons: Remove -Werror for the gem5 v22.1 release While gem5 compiles on all our supported compilers, removing the -Werror flag on the stable branch ensures that, as new compilers are released with stricter warnings, gem5 remains compilable. Change-Id: Ib6d4f86d9c7e60f23eba843e444cdd7812cdde41 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65912 Tested-by: kokoro Reviewed-by: Bobby Bruce Maintainer: Bobby Bruce --- SConstruct | 8 -------- 1 file changed, 8 deletions(-) diff --git a/SConstruct b/SConstruct index bd26e4552e..e8107ea2c7 100755 --- a/SConstruct +++ b/SConstruct @@ -420,14 +420,6 @@ for variant_path in variant_paths: conf.CheckLinkFlag('-Wl,--threads') conf.CheckLinkFlag( '-Wl,--thread-count=%d' % GetOption('num_jobs')) - - # Treat warnings as errors but white list some warnings that we - # want to allow (e.g., deprecation warnings). - env.Append(CCFLAGS=['-Werror', - '-Wno-error=deprecated-declarations', - '-Wno-error=deprecated', - ]) - else: error('\n'.join(( "Don't know what compiler options to use for your compiler.", From 363d65206a8bb85865e019d084aba01b6679a712 Mon Sep 17 00:00:00 2001 From: "Bobby R. Bruce" Date: Mon, 21 Nov 2022 13:52:41 -0800 Subject: [PATCH 27/45] base: Update the version to v22.1.0.0 Change-Id: I4d511a8052cfa5b23e8fecff5e3565b7cfea1763 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65913 Maintainer: Bobby Bruce Tested-by: kokoro Reviewed-by: Bobby Bruce --- src/Doxyfile | 2 +- src/base/version.cc | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/Doxyfile b/src/Doxyfile index 15899099b8..4d14b7ccb7 100644 --- a/src/Doxyfile +++ b/src/Doxyfile @@ -31,7 +31,7 @@ PROJECT_NAME = gem5 # This could be handy for archiving the generated documentation or # if some version control system is used. -PROJECT_NUMBER = DEVELOP-FOR-22.1 +PROJECT_NUMBER = v22.1.0.0 # The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) # base path where the generated documentation will be put. diff --git a/src/base/version.cc b/src/base/version.cc index c5552446af..050aea091f 100644 --- a/src/base/version.cc +++ b/src/base/version.cc @@ -32,6 +32,6 @@ namespace gem5 /** * @ingroup api_base_utils */ -const char *gem5Version = "[DEVELOP-FOR-22.1]"; +const char *gem5Version = "22.1.0.0"; } // namespace gem5 From da2c70af6f9aae9c8308cec11e286e8a6a758288 Mon Sep 17 00:00:00 2001 From: "Bobby R. Bruce" Date: Mon, 21 Nov 2022 13:54:20 -0800 Subject: [PATCH 28/45] python,tests: Update Resource URL path to v22-1 This change ensures the stable branch obtains the right resources for the correct version of gem5. Change-Id: Ie4e90529460d5058a7696d1c1d8f9678563be7bb Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65914 Reviewed-by: Bobby Bruce Tested-by: kokoro Maintainer: Bobby Bruce --- ext/testlib/configuration.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/ext/testlib/configuration.py b/ext/testlib/configuration.py index fd47e3b33a..97c637687d 100644 --- a/ext/testlib/configuration.py +++ b/ext/testlib/configuration.py @@ -213,7 +213,7 @@ def define_defaults(defaults): os.pardir, os.pardir)) defaults.result_path = os.path.join(os.getcwd(), 'testing-results') - defaults.resource_url = 'http://dist.gem5.org/dist/develop' + defaults.resource_url = 'http://dist.gem5.org/dist/v22-1' defaults.resource_path = os.path.abspath(os.path.join(defaults.base_dir, 'tests', 'gem5', From 7185c9ea1936c0045858add1c8c116b15780debc Mon Sep 17 00:00:00 2001 From: "Bobby R. Bruce" Date: Mon, 21 Nov 2022 15:14:10 -0800 Subject: [PATCH 29/45] stdlib: Update the gem5 resources' version to "v22.1" This is required to ensure the correct version of the resources are obtained for this version of gem5. Change-Id: If316081c776d510ec9a2f7ff9e077a1f837d2d2e Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65915 Reviewed-by: Bobby Bruce Tested-by: kokoro Maintainer: Bobby Bruce --- src/python/gem5/resources/downloader.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/python/gem5/resources/downloader.py b/src/python/gem5/resources/downloader.py index 1fda8d86b6..f619b9771d 100644 --- a/src/python/gem5/resources/downloader.py +++ b/src/python/gem5/resources/downloader.py @@ -55,7 +55,7 @@ def _resources_json_version_required() -> str: """ Specifies the version of resources.json to obtain. """ - return "develop" + return "22.1" def _get_resources_json_uri() -> str: From 3df8be981b8a7e961fd0bcd8a20cbd4af9be33ab Mon Sep 17 00:00:00 2001 From: "Bobby R. Bruce" Date: Tue, 22 Nov 2022 13:40:56 -0800 Subject: [PATCH 30/45] util-docker: Update gcn-gpu Docker to use v22-1 ROCM patch Change-Id: I21b530babe095861eb80fdfefd12d8e127ffa3c2 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65916 Reviewed-by: Bobby Bruce Maintainer: Bobby Bruce Tested-by: kokoro --- util/dockerfiles/gcn-gpu/Dockerfile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/dockerfiles/gcn-gpu/Dockerfile b/util/dockerfiles/gcn-gpu/Dockerfile index c5db8963a8..dfff455079 100644 --- a/util/dockerfiles/gcn-gpu/Dockerfile +++ b/util/dockerfiles/gcn-gpu/Dockerfile @@ -69,7 +69,7 @@ RUN git clone -b rocm-4.0.0 \ WORKDIR /ROCclr # The patch allows us to avoid building blit kernels on-the-fly in gem5 -RUN wget -q -O - dist.gem5.org/dist/develop/rocm_patches/ROCclr.patch | git apply -v +RUN wget -q -O - dist.gem5.org/dist/v22-1/rocm_patches/ROCclr.patch | git apply -v WORKDIR /ROCclr/build RUN cmake -DOPENCL_DIR="/ROCm-OpenCL-Runtime" \ From ed6d80c273e791452e0a957941a3f49572c226bb Mon Sep 17 00:00:00 2001 From: "Bobby R. Bruce" Date: Tue, 22 Nov 2022 13:44:31 -0800 Subject: [PATCH 31/45] util-docker: Add v22-1 tag to docker-compose.yaml Change-Id: I91088efe4e0bcee9b9f83d5208a14932821a17c4 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65917 Reviewed-by: Bobby Bruce Maintainer: Bobby Bruce Tested-by: kokoro --- util/dockerfiles/docker-compose.yaml | 50 ++++++++++++++-------------- 1 file changed, 25 insertions(+), 25 deletions(-) diff --git a/util/dockerfiles/docker-compose.yaml b/util/dockerfiles/docker-compose.yaml index f02d6005de..004052283a 100644 --- a/util/dockerfiles/docker-compose.yaml +++ b/util/dockerfiles/docker-compose.yaml @@ -5,154 +5,154 @@ services: build: context: gcn-gpu dockerfile: Dockerfile - image: gcr.io/gem5-test/gcn-gpu + image: gcr.io/gem5-test/gcn-gpu:v22-1 gpu-fs: build: context: gpu-fs dockerfile: Dockerfile - image: gcr.io/gem5-test/gpu-fs + image: gcr.io/gem5-test/gpu-fs:v22-1 sst: build: context: sst-11.1.0 dockerfile: Dockerfile - image: gcr.io/gem5-test/sst-env + image: gcr.io/gem5-test/sst-env:v22-1 systemc: build: context: systemc-2.3.3 dockerfile: Dockerfile - image: gcr.io/gem5-test/systemc-env + image: gcr.io/gem5-test/systemc-env:v22-1 ubuntu-18.04_all-dependencies: build: context: ubuntu-18.04_all-dependencies dockerfile: Dockerfile - image: gcr.io/gem5-test/ubuntu-18.04_all-dependencies + image: gcr.io/gem5-test/ubuntu-18.04_all-dependencies:v22-1 ubuntu-20.04_all-dependencies: build: context: ubuntu-20.04_all-dependencies dockerfile: Dockerfile - image: gcr.io/gem5-test/ubuntu-20.04_all-dependencies + image: gcr.io/gem5-test/ubuntu-20.04_all-dependencies:v22-1 ubuntu-22.04_all-dependencies: build: context: ubuntu-22.04_all-dependencies dockerfile: Dockerfile - image: gcr.io/gem5-test/ubuntu-22.04_all-dependencies + image: gcr.io/gem5-test/ubuntu-22.04_all-dependencies:v22-1 ubuntu-22.04_min-dependencies: build: context: ubuntu-22.04_min-dependencies dockerfile: Dockerfile - image: gcr.io/gem5-test/ubuntu-22.04_min-dependencies + image: gcr.io/gem5-test/ubuntu-22.04_min-dependencies:v22-1 gcc-7: build: context: ubuntu-18.04_gcc-version dockerfile: Dockerfile args: - version=7 - image: gcr.io/gem5-test/gcc-version-7 + image: gcr.io/gem5-test/gcc-version-7:v22-1 gcc-8: build: context: ubuntu-18.04_gcc-version dockerfile: Dockerfile args: - version=8 - image: gcr.io/gem5-test/gcc-version-8 + image: gcr.io/gem5-test/gcc-version-8:v22-1 gcc-9: build: context: ubuntu-20.04_gcc-version dockerfile: Dockerfile args: - version=9 - image: gcr.io/gem5-test/gcc-version-9 + image: gcr.io/gem5-test/gcc-version-9:v22-1 gcc-10: build: context: ubuntu-20.04_gcc-version dockerfile: Dockerfile args: - version=10 - image: gcr.io/gem5-test/gcc-version-10 + image: gcr.io/gem5-test/gcc-version-10:v22-1 gcc-11: build: context: ubuntu-22.04_gcc-version dockerfile: Dockerfile args: - version=11 - image: gcr.io/gem5-test/gcc-version-11 + image: gcr.io/gem5-test/gcc-version-11:v22-1 gcc-12: build: context: ubuntu-22.04_gcc-version dockerfile: Dockerfile args: - version=12 - image: gcr.io/gem5-test/gcc-version-12 + image: gcr.io/gem5-test/gcc-version-12:v22-1 clang-6: build: context: ubuntu-18.04_clang-version dockerfile: Dockerfile args: - version=6.0 - image: gcr.io/gem5-test/clang-version-6.0 + image: gcr.io/gem5-test/clang-version-6.0:v22-1 clang-7: build: context: ubuntu-18.04_clang-version dockerfile: Dockerfile args: - version=7 - image: gcr.io/gem5-test/clang-version-7 + image: gcr.io/gem5-test/clang-version-7:v22-1 clang-8: build: context: ubuntu-18.04_clang-version dockerfile: Dockerfile args: - version=8 - image: gcr.io/gem5-test/clang-version-8 + image: gcr.io/gem5-test/clang-version-8:v22-1 clang-9: build: context: ubuntu-18.04_clang-version dockerfile: Dockerfile args: - version=9 - image: gcr.io/gem5-test/clang-version-9 + image: gcr.io/gem5-test/clang-version-9:v22-1 clang-10: build: context: ubuntu-20.04_clang-version dockerfile: Dockerfile args: - version=10 - image: gcr.io/gem5-test/clang-version-10 + image: gcr.io/gem5-test/clang-version-10:v22-1 clang-11: build: context: ubuntu-20.04_clang-version dockerfile: Dockerfile args: - version=11 - image: gcr.io/gem5-test/clang-version-11 + image: gcr.io/gem5-test/clang-version-11:v22-1 clang-12: build: context: ubuntu-20.04_clang-version dockerfile: Dockerfile args: - version=12 - image: gcr.io/gem5-test/clang-version-12 + image: gcr.io/gem5-test/clang-version-12:v22-1 clang-13: build: context: ubuntu-22.04_clang-version dockerfile: Dockerfile args: - version=13 - image: gcr.io/gem5-test/clang-version-13 + image: gcr.io/gem5-test/clang-version-13:v22-1 clang-14: build: context: ubuntu-22.04_clang-version dockerfile: Dockerfile args: - version=14 - image: gcr.io/gem5-test/clang-version-14 + image: gcr.io/gem5-test/clang-version-14:v22-1 llvm-gnu-cross-compiler-riscv64: build: context: llvm-gnu-cross-compiler-riscv64 dockerfile: Dockerfile - image: gcr.io/gem5-test/llvm-gnu-cross-compiler-riscv64 + image: gcr.io/gem5-test/llvm-gnu-cross-compiler-riscv64:v22-1 gem5-all-min-dependencies: build: context: gem5-all-min-dependencies dockerfile: Dockerfile - image: gcr.io/gem5-test/gem5-all-min-dependencies + image: gcr.io/gem5-test/gem5-all-min-dependencies:v22-1 From d1c72cecb3b45bcf5b792901525717d9a7d882ea Mon Sep 17 00:00:00 2001 From: "Bobby R. Bruce" Date: Mon, 21 Nov 2022 15:27:55 -0800 Subject: [PATCH 32/45] tests: Update the compiler-tests.sh to use the v22-1 images This keeps the running of the compiler tests consistent by using a fixed version of the compiler images. Change-Id: I6e8d8313939696ed22f22e55f9c274c0105ce236 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65918 Reviewed-by: Bobby Bruce Maintainer: Bobby Bruce Tested-by: kokoro --- tests/compiler-tests.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/compiler-tests.sh b/tests/compiler-tests.sh index e01d9de347..57938283b5 100755 --- a/tests/compiler-tests.sh +++ b/tests/compiler-tests.sh @@ -108,7 +108,7 @@ for compiler in ${images[@]}; do # targets for this test build_indices=(${build_permutation[@]:0:$builds_count}) - repo_name="${base_url}/${compiler}:latest" + repo_name="${base_url}/${compiler}:v22-1" # Grab compiler image docker pull $repo_name >/dev/null From 1c79a469baaab326bb5cf89209442b170ce762b0 Mon Sep 17 00:00:00 2001 From: "Bobby R. Bruce" Date: Mon, 21 Nov 2022 15:52:47 -0800 Subject: [PATCH 33/45] tests: Abstract the docker image tag for Nightly tests This abstraction allows us to more easily change the tags between different gem5 releases and/or between stable and the develop branch. Change-Id: Ieb38e9a333ef8592b586014a3a9220f4a18c64e3 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65919 Reviewed-by: Bobby Bruce Tested-by: kokoro Maintainer: Bobby Bruce --- tests/nightly.sh | 26 +++++++++++++++----------- 1 file changed, 15 insertions(+), 11 deletions(-) diff --git a/tests/nightly.sh b/tests/nightly.sh index ec15f91a78..1360c4435c 100755 --- a/tests/nightly.sh +++ b/tests/nightly.sh @@ -35,6 +35,10 @@ gem5_root="${dir}/.." # The per-container Docker memory limit. docker_mem_limit="18g" +# The docker tag to use (varies between develop, and versions on the staging +# branch) +tag="latest" + # The first argument is the number of threads to be used for compilation. If no # argument is given we default to one. compile_threads=1 @@ -66,13 +70,13 @@ unit_test () { docker run -u $UID:$GID --volume "${gem5_root}":"${gem5_root}" -w \ "${gem5_root}" --memory="${docker_mem_limit}" --rm \ - gcr.io/gem5-test/ubuntu-22.04_all-dependencies:latest \ + gcr.io/gem5-test/ubuntu-22.04_all-dependencies:${tag} \ scons build/ALL/unittests.${build} -j${compile_threads} \ --ignore-style } # Ensure we have the latest docker images. -docker pull gcr.io/gem5-test/ubuntu-22.04_all-dependencies:latest +docker pull gcr.io/gem5-test/ubuntu-22.04_all-dependencies:${tag} # Run the unit tests. unit_test opt @@ -81,7 +85,7 @@ unit_test debug # Run the gem5 long tests. docker run -u $UID:$GID --volume "${gem5_root}":"${gem5_root}" -w \ "${gem5_root}"/tests --memory="${docker_mem_limit}" --rm \ - gcr.io/gem5-test/ubuntu-22.04_all-dependencies:latest \ + gcr.io/gem5-test/ubuntu-22.04_all-dependencies:${tag} \ ./main.py run --length long -j${compile_threads} -t${run_threads} -vv # Unfortunately, due docker being unable run KVM, we do so separately. @@ -101,10 +105,10 @@ cd "${gem5_root}/tests" cd "${gem5_root}" # For the GPU tests we compile and run the GPU ISA inside a gcn-gpu container. -docker pull gcr.io/gem5-test/gcn-gpu:latest +docker pull gcr.io/gem5-test/gcn-gpu:${tag} docker run --rm -u $UID:$GID --volume "${gem5_root}":"${gem5_root}" -w \ "${gem5_root}" --memory="${docker_mem_limit}" \ - gcr.io/gem5-test/gcn-gpu:latest bash -c \ + gcr.io/gem5-test/gcn-gpu:${tag} bash -c \ "scons build/${gpu_isa}/gem5.opt -j${compile_threads} --ignore-style \ || (rm -rf build && scons build/${gpu_isa}/gem5.opt \ -j${compile_threads} --ignore-style)" @@ -119,7 +123,7 @@ mkdir -p tests/testing-results # basic GPU functionality is working. docker run --rm -u $UID:$GID --volume "${gem5_root}":"${gem5_root}" -w \ "${gem5_root}" --memory="${docker_mem_limit}" \ - gcr.io/gem5-test/gcn-gpu:latest build/${gpu_isa}/gem5.opt \ + gcr.io/gem5-test/gcn-gpu:${tag} build/${gpu_isa}/gem5.opt \ configs/example/apu_se.py --reg-alloc-policy=dynamic -n3 -c square # get HeteroSync @@ -131,7 +135,7 @@ wget -qN http://dist.gem5.org/dist/develop/test-progs/heterosync/gcn3/allSyncPri # atomics are tested. docker run --rm -u $UID:$GID --volume "${gem5_root}":"${gem5_root}" -w \ "${gem5_root}" --memory="${docker_mem_limit}" \ - gcr.io/gem5-test/gcn-gpu:latest build/${gpu_isa}/gem5.opt \ + gcr.io/gem5-test/gcn-gpu:${tag} build/${gpu_isa}/gem5.opt \ configs/example/apu_se.py --reg-alloc-policy=dynamic -n3 -c \ allSyncPrims-1kernel --options="sleepMutex 10 16 4" @@ -142,7 +146,7 @@ docker run --rm -u $UID:$GID --volume "${gem5_root}":"${gem5_root}" -w \ # atomics are tested. docker run --rm -u $UID:$GID --volume "${gem5_root}":"${gem5_root}" -w \ "${gem5_root}" --memory="${docker_mem_limit}" \ - gcr.io/gem5-test/gcn-gpu:latest build/${gpu_isa}/gem5.opt \ + gcr.io/gem5-test/gcn-gpu:${tag} build/${gpu_isa}/gem5.opt \ configs/example/apu_se.py --reg-alloc-policy=dynamic -n3 -c \ allSyncPrims-1kernel --options="lfTreeBarrUniq 10 16 4" @@ -153,7 +157,7 @@ build_and_run_SST () { docker run -u $UID:$GID --volume "${gem5_root}":"${gem5_root}" -w \ "${gem5_root}" --rm --memory="${docker_mem_limit}" \ - gcr.io/gem5-test/sst-env:latest bash -c "\ + gcr.io/gem5-test/sst-env:${tag} bash -c "\ scons build/${isa}/libgem5_${variant}.so -j${compile_threads} \ --without-tcmalloc --ignore-style; \ cd ext/sst; \ @@ -168,7 +172,7 @@ build_and_run_systemc () { rm -rf "${gem5_root}/build/ARM" docker run -u $UID:$GID --volume "${gem5_root}":"${gem5_root}" -w \ "${gem5_root}" --memory="${docker_mem_limit}" --rm \ - gcr.io/gem5-test/ubuntu-22.04_all-dependencies:latest bash -c "\ + gcr.io/gem5-test/ubuntu-22.04_all-dependencies:${tag} bash -c "\ scons -j${compile_threads} --ignore-style build/ARM/gem5.opt; \ scons --with-cxx-config --without-python --without-tcmalloc USE_SYSTEMC=0 \ -j${compile_threads} build/ARM/libgem5_opt.so \ @@ -176,7 +180,7 @@ scons --with-cxx-config --without-python --without-tcmalloc USE_SYSTEMC=0 \ docker run -u $UID:$GID --volume "${gem5_root}":"${gem5_root}" -w \ "${gem5_root}" --memory="${docker_mem_limit}" --rm \ - gcr.io/gem5-test/systemc-env:latest bash -c "\ + gcr.io/gem5-test/systemc-env:${tag} bash -c "\ cd util/systemc/gem5_within_systemc; \ make -j${compile_threads}; \ ../../../build/ARM/gem5.opt ../../../configs/example/se.py -c \ From 1e5bd5b89ac1eeeba22a38664126e553faa422c1 Mon Sep 17 00:00:00 2001 From: "Bobby R. Bruce" Date: Mon, 21 Nov 2022 15:56:06 -0800 Subject: [PATCH 34/45] tests: Update nightly test docker image tags to v22-1 Change-Id: I3d1fa67a89594050cb8069541004763ac5ba66a4 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65920 Reviewed-by: Bobby Bruce Maintainer: Bobby Bruce Tested-by: kokoro --- tests/nightly.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/nightly.sh b/tests/nightly.sh index 1360c4435c..bf05154fe7 100755 --- a/tests/nightly.sh +++ b/tests/nightly.sh @@ -37,7 +37,7 @@ docker_mem_limit="18g" # The docker tag to use (varies between develop, and versions on the staging # branch) -tag="latest" +tag="v22-1" # The first argument is the number of threads to be used for compilation. If no # argument is given we default to one. From 38778c5a172b237c39dbdd928084e534877aaee1 Mon Sep 17 00:00:00 2001 From: "Bobby R. Bruce" Date: Mon, 21 Nov 2022 16:00:28 -0800 Subject: [PATCH 35/45] tests: Abstract the docker image tag for Weekly tests This abstraction allows us to more easily change the tags between different gem5 releases and/or between stable and the develop branch. Change-Id: Iad49cabac9b4000e8570162d3e12453c6d097ee2 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65921 Reviewed-by: Bobby Bruce Maintainer: Bobby Bruce Tested-by: kokoro --- tests/weekly.sh | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/tests/weekly.sh b/tests/weekly.sh index 3d8af297e5..c7f834b7a5 100755 --- a/tests/weekly.sh +++ b/tests/weekly.sh @@ -35,6 +35,10 @@ gem5_root="${dir}/.." # The per-container Docker memory limit. docker_mem_limit="24g" +# The docker tag to use (varies between develop, and versions on the staging +# branch) +tag="latest" + # We assume the first two arguments are the number of threads followed by the # GPU ISA to test. These default to 1 and GCN3_X86 is no argument is given. threads=1 @@ -59,7 +63,7 @@ fi # Run the gem5 very-long tests. docker run -u $UID:$GID --volume "${gem5_root}":"${gem5_root}" -w \ "${gem5_root}"/tests --memory="${docker_mem_limit}" --rm \ - gcr.io/gem5-test/ubuntu-22.04_all-dependencies:latest \ + gcr.io/gem5-test/ubuntu-22.04_all-dependencies:${tag} \ ./main.py run --length very-long -j${threads} -t${threads} -vv mkdir -p tests/testing-results @@ -68,7 +72,7 @@ mkdir -p tests/testing-results # before pulling gem5 resources, make sure it doesn't exist already docker run --rm --volume "${gem5_root}":"${gem5_root}" -w \ "${gem5_root}" --memory="${docker_mem_limit}" \ - gcr.io/gem5-test/gcn-gpu:latest bash -c \ + gcr.io/gem5-test/gcn-gpu:${tag} bash -c \ "rm -rf ${gem5_root}/gem5-resources" # delete Pannotia datasets and output files in case a failed regression run left # them around @@ -113,7 +117,7 @@ cd "${gem5_root}" # avoid needing to set all of these, we instead build a docker for it, which # has all these variables pre-set in its Dockerfile # To avoid compiling gem5 multiple times, all GPU benchmarks will use this -docker pull gcr.io/gem5-test/gcn-gpu:latest +docker pull gcr.io/gem5-test/gcn-gpu:${tag} docker build -t hacc-test-weekly ${gem5_root}/gem5-resources/src/gpu/halo-finder docker run --rm -u $UID:$GID --volume "${gem5_root}":"${gem5_root}" -w \ From 1c422628bc9dcbc3f24c77d456fdd3653e34b8e7 Mon Sep 17 00:00:00 2001 From: "Bobby R. Bruce" Date: Mon, 21 Nov 2022 16:04:02 -0800 Subject: [PATCH 36/45] tests: Update weekly test docker image tags to v22-1 Change-Id: I6a7ff942234f65b763d2974deb740942bfc2cc17 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65922 Reviewed-by: Bobby Bruce Maintainer: Bobby Bruce Tested-by: kokoro --- tests/weekly.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/weekly.sh b/tests/weekly.sh index c7f834b7a5..9b400b9a83 100755 --- a/tests/weekly.sh +++ b/tests/weekly.sh @@ -37,7 +37,7 @@ docker_mem_limit="24g" # The docker tag to use (varies between develop, and versions on the staging # branch) -tag="latest" +tag="v22-1" # We assume the first two arguments are the number of threads followed by the # GPU ISA to test. These default to 1 and GCN3_X86 is no argument is given. From a3fd9631cc209914fad2e2c1fb24006d6d5adc2d Mon Sep 17 00:00:00 2001 From: "Bobby R. Bruce" Date: Fri, 2 Dec 2022 11:15:45 -0800 Subject: [PATCH 37/45] util-gem5art: Fix incorrect type of size in `createArtifact` The typing here was `int` but had a default value of `None`. The correct type is therefore `Optional[int]`. Change-Id: Ibaf63151196b15f68e643fa5c1b290439d6618c8 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66371 Maintainer: Bobby Bruce Tested-by: kokoro Reviewed-by: Bobby Bruce --- util/gem5art/artifact/gem5art/artifact/artifact.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/gem5art/artifact/gem5art/artifact/artifact.py b/util/gem5art/artifact/gem5art/artifact/artifact.py index 91ffc64e50..46664e82fb 100644 --- a/util/gem5art/artifact/gem5art/artifact/artifact.py +++ b/util/gem5art/artifact/gem5art/artifact/artifact.py @@ -158,7 +158,7 @@ class Artifact: documentation: str, inputs: List["Artifact"] = [], architecture: str = "", - size: int = None, + size: Optional[int] = None, is_zipped: bool = False, md5sum: str = "", url: str = "", From 620e5243e7dad39eb3bae340384db8400a0acaed Mon Sep 17 00:00:00 2001 From: "Bobby R. Bruce" Date: Mon, 21 Nov 2022 16:07:44 -0800 Subject: [PATCH 38/45] tests: Update presubmit.sh to use v22-1 docker images Change-Id: I7b800f794af699281f17d6c484393c1646e3de4e Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65923 Maintainer: Bobby Bruce Reviewed-by: Bobby Bruce Tested-by: kokoro --- tests/jenkins/presubmit.sh | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tests/jenkins/presubmit.sh b/tests/jenkins/presubmit.sh index 91eb95f81b..36da3facd1 100755 --- a/tests/jenkins/presubmit.sh +++ b/tests/jenkins/presubmit.sh @@ -37,8 +37,8 @@ set -e -DOCKER_IMAGE_ALL_DEP=gcr.io/gem5-test/ubuntu-22.04_all-dependencies:latest -DOCKER_IMAGE_CLANG_COMPILE=gcr.io/gem5-test/clang-version-14:latest +DOCKER_IMAGE_ALL_DEP=gcr.io/gem5-test/ubuntu-22.04_all-dependencies:v22-1 +DOCKER_IMAGE_CLANG_COMPILE=gcr.io/gem5-test/clang-version-14:v22-1 PRESUBMIT_STAGE2=tests/jenkins/presubmit-stage2.sh GEM5ART_TESTS=tests/jenkins/gem5art-tests.sh From e200ea1510e337a001754bcf299c6dea74e36186 Mon Sep 17 00:00:00 2001 From: "Bobby R. Bruce" Date: Mon, 21 Nov 2022 16:11:07 -0800 Subject: [PATCH 39/45] ext: Update ext/sst/README.md for v22.1 release Change-Id: I3221bbc4e4bf1d7a2bd7516873c7bfcf08bebde5 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65924 Tested-by: kokoro Reviewed-by: Bobby Bruce Maintainer: Bobby Bruce --- ext/sst/README.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/ext/sst/README.md b/ext/sst/README.md index d9bbe85e1b..49f56349bb 100644 --- a/ext/sst/README.md +++ b/ext/sst/README.md @@ -62,7 +62,7 @@ See `INSTALL.md`. Downloading the built bootloader containing a Linux Kernel and a workload, ```sh -wget http://dist.gem5.org/dist/v22-0/misc/riscv/bbl-busybox-boot-exit +wget http://dist.gem5.org/dist/v22-1/misc/riscv/bbl-busybox-boot-exit ``` Running the simulation @@ -87,7 +87,7 @@ extract them under the $M5_PATH directory (make sure M5_PATH points to a valid directory): ```sh -wget http://dist.gem5.org/dist/v22-0/arm/aarch-sst-20211207.tar.bz2 +wget http://dist.gem5.org/dist/v22-1/arm/aarch-sst-20211207.tar.bz2 tar -xf aarch-sst-20211207.tar.bz2 # copying bootloaders From 1e73beb620913e0088fdeacc0fa5787de03cd867 Mon Sep 17 00:00:00 2001 From: "Bobby R. Bruce" Date: Mon, 5 Dec 2022 15:28:00 -0800 Subject: [PATCH 40/45] python: Remove 'scheduleTickExit' in favor of 'exitSimLoop' The commit https://gem5-review.googlesource.com/c/public/gem5/+/66231 added an API to m5 for scheduling to-tick exit events. This added the function `schedule_tick_exit`. It was later pointed out that this `schedule_tick_exit` event is redundant given the existance of `exitSimLoop`. This patch therefore removes `schedule_tick_exit` in favor of `exitSimLoop`. Change-Id: Ibecf00b98256a5da2868427d766bdc93f03c3f97 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66511 Tested-by: kokoro Reviewed-by: Bobby Bruce Maintainer: Bobby Bruce --- src/python/m5/simulate.py | 2 +- src/python/pybind11/event.cc | 2 -- src/sim/simulate.cc | 5 ----- src/sim/simulate.hh | 10 ---------- 4 files changed, 1 insertion(+), 18 deletions(-) diff --git a/src/python/m5/simulate.py b/src/python/m5/simulate.py index 744d95f9f6..18fb1d6cd4 100644 --- a/src/python/m5/simulate.py +++ b/src/python/m5/simulate.py @@ -259,7 +259,7 @@ def scheduleTickExitAbsolute( """ if tick <= curTick(): warn("Tick exit scheduled for the past. This will not be triggered.") - _m5.event.scheduleTickExit(tick=tick, exit_string=exit_string) + _m5.event.exitSimLoop(exit_string, 0, tick, 0, False) def drain(): diff --git a/src/python/pybind11/event.cc b/src/python/pybind11/event.cc index 827768f52f..95e6ddb844 100644 --- a/src/python/pybind11/event.cc +++ b/src/python/pybind11/event.cc @@ -109,8 +109,6 @@ pybind_init_event(py::module_ &m_native) py::arg("ticks") = MaxTick); m.def("setMaxTick", &set_max_tick, py::arg("tick")); m.def("getMaxTick", &get_max_tick, py::return_value_policy::copy); - m.def("scheduleTickExit", &schedule_tick_exit, py::arg("tick"), - py::arg("exit_string")); m.def("terminateEventQueueThreads", &terminateEventQueueThreads); m.def("exitSimLoop", &exitSimLoop); m.def("getEventQueue", []() { return curEventQueue(); }, diff --git a/src/sim/simulate.cc b/src/sim/simulate.cc index 4993859036..95b2c05618 100644 --- a/src/sim/simulate.cc +++ b/src/sim/simulate.cc @@ -263,11 +263,6 @@ Tick get_max_tick() return simulate_limit_event->when(); } -void schedule_tick_exit(Tick tick, std::string exit_string) -{ - new GlobalSimLoopExitEvent(tick, exit_string, 0); -} - void terminateEventQueueThreads() { diff --git a/src/sim/simulate.hh b/src/sim/simulate.hh index e7c4fa640c..eacf67cec2 100644 --- a/src/sim/simulate.hh +++ b/src/sim/simulate.hh @@ -67,16 +67,6 @@ void set_max_tick(Tick tick); */ Tick get_max_tick(); -/** - * @brief Schedule an exit event at a particular tick. - * - * Schedule a tick with a particular exit string. - * - * @param tick The tick at which the simulation loop should exit. - * @param exit_string The exit string explaining the exit. - */ -void schedule_tick_exit(Tick tick, std::string exit_string); - /** * Terminate helper threads when running in parallel mode. * From 5d475506d7322bdd309c265776de3b3fd50a606d Mon Sep 17 00:00:00 2001 From: "Bobby R. Bruce" Date: Tue, 6 Dec 2022 10:39:18 -0800 Subject: [PATCH 41/45] configs: Fix x86-gapbs-benchmarks.py example With https://gem5-review.googlesource.com/c/public/gem5/+/64791 we updated the configs/example/gem5_library to utilize the `m5.simulate` module. The GAPBS benchmark example uses the "WORKBEGIN" and "WORKEND" exit events to specify the ROI. The patch incorrectly assumed an "EXIT" exit event were used. As such, the "test-gem5-library-example-x86-gapbs-benchmarks-ALL-x86_64-opt-MESI_Two_Level" test was not properly running, causing the Nightly test to fail: https://jenkins.gem5.org/job/nightly/444. This patch fixes this error. Change-Id: I207fe3563c8d9c59bcb79428fe62d2d2bbccd013 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66514 Tested-by: kokoro Reviewed-by: Bobby Bruce Maintainer: Bobby Bruce --- configs/example/gem5_library/x86-gapbs-benchmarks.py | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/configs/example/gem5_library/x86-gapbs-benchmarks.py b/configs/example/gem5_library/x86-gapbs-benchmarks.py index 638d34b599..6ab37479f9 100644 --- a/configs/example/gem5_library/x86-gapbs-benchmarks.py +++ b/configs/example/gem5_library/x86-gapbs-benchmarks.py @@ -211,7 +211,7 @@ board.set_kernel_disk_workload( ) -def handle_exit(): +def handle_workbegin(): print("Done booting Linux") print("Resetting stats at the start of ROI!") m5.stats.reset() @@ -219,6 +219,9 @@ def handle_exit(): start_tick = m5.curTick() processor.switch() yield False # E.g., continue the simulation. + + +def handle_workend(): print("Dump stats at the end of the ROI!") m5.stats.dump() yield True # Stop the simulation. We're done. @@ -227,7 +230,8 @@ def handle_exit(): simulator = Simulator( board=board, on_exit_event={ - ExitEvent.EXIT: handle_exit(), + ExitEvent.WORKBEGIN: handle_workbegin(), + ExitEvent.WORKEND: handle_workend(), }, ) From c765cfb64b1eebd2988192f7550ef9df5e0f77e3 Mon Sep 17 00:00:00 2001 From: "Bobby R. Bruce" Date: Tue, 6 Dec 2022 10:48:48 -0800 Subject: [PATCH 42/45] configs: Alter x86-npb-benchmarks.py to exit after WORKEND While the config script will still function without exiting the SimLoop after the "WORKEND" exit event, there's no need for the simulation to continue beyond this point. Change-Id: I60691215e9516fa1eeb8b8502f2bc5a09de2969b Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66515 Maintainer: Bobby Bruce Reviewed-by: Bobby Bruce Tested-by: kokoro --- configs/example/gem5_library/x86-npb-benchmarks.py | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/configs/example/gem5_library/x86-npb-benchmarks.py b/configs/example/gem5_library/x86-npb-benchmarks.py index 2cb314303f..ff363e449c 100644 --- a/configs/example/gem5_library/x86-npb-benchmarks.py +++ b/configs/example/gem5_library/x86-npb-benchmarks.py @@ -237,12 +237,11 @@ def handle_workbegin(): # marked by `workend`. # We exepect that ROI ends with `workend` or `simulate() limit reached`. -# Otherwise the simulation ended unexpectedly. def handle_workend(): print("Dump stats at the end of the ROI!") m5.stats.dump() - yield False + yield True simulator = Simulator( From 81cb7c05b4a514c75d41b86217d5e0feb148a4ef Mon Sep 17 00:00:00 2001 From: "Bobby R. Bruce" Date: Tue, 6 Dec 2022 14:13:40 -0800 Subject: [PATCH 43/45] misc: Update .mailmap This commit updates the mailmap since the initial commit in mid-July 2020: https://gem5-review.googlesource.com/c/public/gem5/+/29672. `sort -u` has been run on this file so some previous entries have been moved. Change-Id: I46df1e9675f6f7057b680ca2abbcebdffd50462a Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66531 Tested-by: kokoro Reviewed-by: Bobby Bruce Maintainer: Bobby Bruce --- .mailmap | 221 ++++++++++++++++++++++++++++++++++++++++--------------- 1 file changed, 160 insertions(+), 61 deletions(-) diff --git a/.mailmap b/.mailmap index 5125666bbc..49c438d3eb 100644 --- a/.mailmap +++ b/.mailmap @@ -1,37 +1,43 @@ -ARM gem5 Developers Abdul Mutaal Ahmad +adarshpatil +Adrià Armejach Adrià Armejach Adrian Herrera Adrien Pesle -Adrià Armejach Adrià Armejach Akash Bagdia Akash Bagdia Alec Roelke Alec Roelke +Alexander Klimov Alexandru Dutu Alexandru +Alex Richardson Ali Jafri -Ali Saidi Ali Saidi Ali Saidi Ali Saidi +Ali Saidi Ali Saidi Ali Saidi Ali Saidi +Alistair Delva Amin Farmahini Anders Handler -Andrea Mondelli Andrea Mondelli +Andrea Mondelli Andrea Mondelli +Andrea Mondelli Andrea Mondelli Andrea Pellegrini -Andreas Hansson Andreas Hansson Andreas Hansson Andreas Hansson Andreas Hansson Andreas Hansson +Andreas Hansson Andreas Hansson Andreas Hansson Andreas Hansson -Andreas Sandberg Andreas Sandberg Andreas Sandberg Andreas Sandberg +Andreas Sandberg Andreas Sandberg Andreas Sandberg Andreas Sandberg Andrew Bardsley Andrew Bardsley Andrew Lukefahr Andrew Schultz Andriani Mappoura -Ani Udipi +Angie Lee Anis Peysieux +Ani Udipi Anouk Van Laer -Arthur Perais +ARM gem5 Developers +Arthur Perais Arthur Perais +Arun Rodrigues Ashkan Tousi -Austin Harris -Richard D. Strong +Austin Harris Austin Harris Avishai Tvila Ayaz Akram Bagus Hanindhito @@ -41,80 +47,108 @@ Binh Pham Bjoern A. Zeeb Blake Hechtman Blake Hechtman Blake Hechtman Blake Hechtman ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E) -Bobby R. Bruce +Bobby R. Bruce Bobby Bruce Boris Shingarov Boris Shingarov Brad Beckmann Brad Beckmann Brad Beckmann Brad Beckmann ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E) Brad Danofsky Bradley Wang Bradley +Brandon Potter BKP Brandon Potter bpotter Brandon Potter Brandon Potter -Brandon Potter BKP Brian Grayson Cagdas Dirik cdirik +Carlos Falquez Chander Sudanthi Chander Sudanthi Chander Sudanthi Chander Sudanthi +Charles Jamieson +CHEN Meng Chen Zou +Chia-You Chen +Chow, Marcus Chris Adeniyi-Jones -Chris Emmons Chris Emmons Chris Emmons Chris Emmons +Chris Emmons Chris Emmons +Chris January Christian Menard Christian Menard -Christoph Pfister Christopher Torng +Christoph Pfister Chuan Zhu Chun-Chen Hsu Chun-Chen TK Hsu Ciro Santilli Clint Smullen +Cui Jin Cui Jin Curtis Dunham +Daecheol You Dam Sunwoo Dan Gibson Daniel Carvalho Daniel Daniel Carvalho Daniel R. Carvalho +Daniel Gerzhoy Daniel Johnson Daniel Sanchez +Davide Basilio Bartolini David Guillen-Fandos David Guillen David Guillen-Fandos David Guillen Fandos David Hashe David Hashe David Oehmke +David Schall +Derek Christ Derek Hower -Deyaun Guo Deyuan Guo Deyaun Guo Deyuan Guo ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E) +Deyaun Guo Deyuan Guo Dibakar Gope Dibakar Gope ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E) +Dimitrios Chasapis Djordje Kovacevic Djordje Kovacevic -Dongxue Zhang Doğukan Korkmaztürk +Dongxue Zhang Dylan Johnson Earl Ou +eavivi +Éder F. Zulian Edmund Grimley Evans +Eduardo José Gómez Hernández +Eliot Moss Emilio Castillo Emilio Castillo Emilio Castillo Emilio Castillo ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E) +Emily Brickey Erfan Azarkhish +Erhu Eric Van Hensbergen Eric Van Hensbergen +Eric Ye Erik Hallnor Erik Tomusk Faissal Sleiman Faissal Sleiman Fernando Endo +Franklin He Gabe Black Gabe Black Gabe Black Gabe Black +Gabe Loh gloh Gabor Dozsa +Gabriel Busnot +gauravjain14 Gedare Bloom Gedare Bloom Gene Wu Gene WU Gene WU Gene Wu -Geoffrey Blake Geoffrey Blake Geoffrey Blake Geoffrey Blake +Geoffrey Blake Geoffrey Blake Georg Kotheimer Giacomo Gabrielli Giacomo Gabrielli Giacomo Travaglini Glenn Bergmans +GWDx Hamid Reza Khaleghzadeh Hamid Reza Khaleghzadeh ext:(%2C%20Lluc%20Alvarez%20%3Clluc.alvarez%40bsc.es%3E%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E) +handsomeliu Hanhwi Jang Hoa Nguyen Hongil Yoon Hsuan Hsu +huangjs Hussein Elnawawy Ian Jiang IanJiangICT Ilias Vougioukas +Iru Cai Isaac Richter Isaac Sánchez Barrera Ivan Pizarro @@ -123,104 +157,152 @@ Jairo Balart Jakub Jermar James Clarkson Jan-Peter Larsson -Jason Lowe-Power Jason Lowe-Power +Jan Vrany +Jarvis Jia +Jasjeet Rangi Jason Lowe-Power Jason Lowe-Power -Jason Lowe-Power Jason Power -Jason Lowe-Power Jason Power +Jason Lowe-Power Jason Lowe-Power Jason Lowe-Power Jason Power ext:(%2C%20Joel%20Hestness%20%3Chestness%40cs.wisc.edu%3E) +Jason Lowe-Power Jason Power +Jason Lowe-Power Jason Power +Jason Yu Javier Bueno Hedo Javier Bueno Javier Cano-Cano +Javier Garcia Hernandez Javier Setoain Jayneel Gandhi Jennifer Treichler -Jieming Yin +Jerin Joy +Jiajie Chen +Jiasen Huang +Jiasen +Jiayi Huang +jiegec +Jieming Yin jiemingyin Jing Qu JingQuJQ Jiuyue Ma Joe Gross Joe Gross +Joel Hestness Joel Hestness ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E) Joel Hestness Joel Hestness Joel Hestness Joel Hestness -Joel Hestness Joel Hestness ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E) +Joël Porquet-Lupine John Alsop John Kalamatianos jkalamat Jordi Vaquero Jose Marinho +Juan M. Cebrian Jui-min Lee +kai.ren Kai Ren Kanishk Sugand Karthik Sangaiah +Kaustav Goswami +Kelly Nguyen Ke Meng Kevin Brodsky Kevin Lim +Kevin Loughlin Khalique Koan-Sin Tan Korey Sewell Krishnendra Nathella Krishnendra Nathella +ksco +kunpai +Kyle Roarty Kyle Roarty +Laura Hinman Lena Olson Lena Olson Lena Olson Lena Olson Lisa Hsu Lisa Hsu Lluc Alvarez Lluís Vilanova Lluis Vilanova +Lukas Steiner +Luming Wang +m5test Mahyar Samani +Majid Jalili Malek Musleh Nilay Vaish ext:(%2C%20Malek%20Musleh%20%3Cmalek.musleh%40gmail.com%3E) Marc Mari Barcelo -Marc Orr Marc Orr Marco Balboni Marco Elver Marco Elver +Marc Orr Marc Orr +Marjan Fariborz marjanfariborz +Mark Hildebrand +Marton Erdos +Maryam Babaie Matt DeVuyst -Matt Evans Matt Evans -Matt Horsnell Matt Horsnell -Matt Horsnell Matt Horsnell -Matt Horsnell Matt Horsnell -Matt Poremba Matt Poremba Matteo Andreozzi Matteo Andreozzi Matteo M. Fusi +Matt Evans Matt Evans Matthew Poremba Matthew Poremba -Matt Sinclair Matthew Sinclair Matthias Hille Matthias Jung +Matthias Jung +Matt Horsnell Matt Horsnell +Matt Horsnell Matt Horsnell +Matt Horsnell Matt Horsnell +Matt Poremba Matt Poremba +Matt Sinclair Matthew Sinclair +Matt Sinclair Matt Sinclair Maurice Becker Maxime Martinasso -Maximilian Stein +Maximilian Stein Maximilian Stein Maximilien Breughe Maximilien Breughe +Melissa Jost Michael Adler +Michael Boyer Michael LeBeane Michael LeBeane Michael LeBeane mlebeane Michael Levenhagen -Michiel Van Tol Michiel W. van Tol Michiel Van Tol Michiel van Tol +Michiel Van Tol Michiel W. van Tol Miguel Serrano +Mike Upton Miles Kaufmann -Min Kyu Jeong Min Kyu Jeong Mingyuan -Mitch Hayenga Mitch Hayenga -Mitch Hayenga Mitch Hayenga -Mitch Hayenga Mitch Hayenga -Mitch Hayenga Mitch Hayenga ext:(%2C%20Amin%20Farmahini%20%3Caminfar%40gmail.com%3E) +Min Kyu Jeong Min Kyu Jeong Mitch Hayenga Mitchell Hayenga +Mitch Hayenga Mitch Hayenga ext:(%2C%20Amin%20Farmahini%20%3Caminfar%40gmail.com%3E) +Mitch Hayenga Mitch Hayenga +Mitch Hayenga Mitch Hayenga +Mitch Hayenga Mitch Hayenga Mohammad Alian Monir Mozumder Moyang Wang Mrinmoy Ghosh Mrinmoy Ghosh -Nathan Binkert Nathan Binkert +Muhammad Sarmad Saeed +Nadia Etemadi Nathanael Premillieu Nathanael Premillieu +Nathanael Premillieu Nathanael Premillieu Nathanael Premillieu Nathanael Premillieu Nathanael Premillieu Nathanael Premillieu Nathanael Premillieu Nathanael Premillieu +Nathan Binkert Nathan Binkert Nayan Deshmukh Neha Agarwal +Neil Natekar Nicholas Lindsay +Nicolas Boichat Nicolas Derumigny Nicolas Zea Nikos Nikoleris Nikos Nikoleris +Nilay Vaish ext:(%2C%20Timothy%20Jones%20%3Ctimothy.jones%40cl.cam.ac.uk%3E) Nils Asmussen Nils Asmussen +Noah Katz +ntampouratzis Nuwan Jayasena Ola Jeppsson Omar Naji +Onur Kayiran Pablo Prieto +paikunal Palle Lyckegaard Pau Cabre Paul Rosenfeld Paul Rosenfeld Paul Rosenfeld Paul Rosenfeld Peter Enns Pierre-Yves Péneau +Peter +Peter Yuen +Philip Metzler +Pierre Ayoub Pin-Yen Lin Po-Hao Su Polina Dudnik Polina Dudnik @@ -229,23 +311,26 @@ Pouya Fotouhi Pouya Fotouhi Prakash Ramrakhyani Prakash Ramrakhani Prakash Ramrakhyani Prakash Ramrakhyani Pritha Ghoshal +Quentin Forcioli Radhika Jagtap Radhika Jagtap Rahul Thakur Reiley Jeapaul -Rekai Gonzalez-Alberquilla Rekai -Rekai Gonzalez-Alberquilla Rekai Gonzalez Alberquilla Rekai Gonzalez-Alberquilla Rekai Gonzalez Alberquilla +Rekai Gonzalez-Alberquilla Rekai Gonzalez Alberquilla Rekai Gonzalez-Alberquilla Rekai Gonzalez-Alberquilla +Rekai Gonzalez-Alberquilla Rekai Rene de Jong Ricardo Alves +Richard Cooper +Richard D. Strong Richard Strong Richard Strong Richard Strong Richard Strong Richard Strong Rick Strong Rico Amslinger Riken Gohil Rizwana Begum -Robert Scheffel Robert Robert Kovacsics +Robert Scheffel Robert Rohit Kurup Ron Dreslinski Ronald Dreslinski Ruben Ayrapetyan @@ -253,20 +338,27 @@ Rune Holm Ruslan Bukin Ruslan Bukin ext:(%2C%20Zhang%20Guoye) Rutuja Oza Ryan Gambord +sacak32 +Sampad Mohapatra Samuel Grayson -Sandipan Das +Samuel Stark +Sandipan Das <31861871+sandip4n@users.noreply.github.com> +Sandipan Das Sandipan Das <31861871+sandip4n@users.noreply.github.com> Santi Galan -Sascha Bischoff Sascha Bischoff Sascha Bischoff Sascha Bischoff +Sascha Bischoff Sascha Bischoff Sean McGoogan Sean Wilson Sergei Trofimov Severin Wischmann Severin Wischmann ext:(%2C%20Ioannis%20Ilkos%20%3Cioannis.ilkos09%40imperial.ac.uk%3E) Shawn Rosti Sherif Elhabbal +Shivani Parekh +Shivani Siddhesh Poyarekar Somayeh Sardashti Sooraj Puthoor +Sooraj Puthoor Sophiane Senni Soumyaroop Roy Srikant Bharadwaj @@ -275,13 +367,14 @@ Stanislaw Czerniawski Stephan Diestelhorst Stephan Diestelhorst Stephen Hines Steve Raasch -Steve Reinhardt Steve Reinhardt -Steve Reinhardt Steve Reinhardt -Steve Reinhardt Steve Reinhardt Steve Reinhardt Steve Reinhardt ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E%2C%20Ali%20Saidi%20%3CAli.Saidi%40ARM.com%3E) +Steve Reinhardt Steve Reinhardt +Steve Reinhardt Steve Reinhardt +Steve Reinhardt Steve Reinhardt Stian Hvatum Sudhanshu Jha Sujay Phadke +Sungkeun Kim Swapnil Haria Swapnil Haria Taeho Kgil Tao Zhang @@ -290,44 +383,50 @@ Tiago Mück Tiago Muck Tim Harris Timothy Hayes Timothy M. Jones Timothy Jones -Timothy M. Jones Nilay Vaish ext:(%2C%20Timothy%20Jones%20%3Ctimothy.jones%40cl.cam.ac.uk%3E) Timothy M. Jones Timothy M. Jones Timothy M. Jones Timothy M. Jones Tom Jablin Tommaso Marinelli +Tom Rollet +Tong Shen Tony Gutierrez Anthony Gutierrez -Tuan Ta Tuan Ta -Tushar Krishna Tushar Krishna +Travis Boraten +Trivikram Reddy tv-reddy +Tuan Ta Tuan Ta Tuan Ta Tushar Krishna Tushar Krishna +Tushar Krishna Tushar Krishna Umesh Bhaskar Uri Wiener Victor Garcia Vilas Sridharan -Vince Weaver Vincentius Robby +Vince Weaver +vramadas95 +vsoria Wade Walker +Wei-Han Chen Weiping Liao +Wende Tan Wendy Elsasser -William Wang William Wang William Wang William Wang +William Wang William Wang Willy Wolff +Wing Li Xiangyu Dong -Xianwei Zhang +Xianwei Zhang Xianwei Zhang Xiaoyu Ma Xin Ouyang +Xiongfei Yasuko Eckert -Yi Xiang +Yen-lin Lai Yifei Liu -Yu-hsin Wang +yiwkd2 +Yi Xiang Yuan Yao Yuetsu Kodama yuetsu.kodama +Yu-hsin Wang Zhang Zheng +Zhantong Qiu +Zhengrong Wang seanzw +zhongchengyong Zicong Wang -Éder F. Zulian -Gabe Loh gloh -jiegec -m5test -Marjan Fariborz marjanfariborz -Mike Upton -seanzw -Trivikram Reddy tv-reddy From 55d821971727519c6df5cd2d50d167944510036d Mon Sep 17 00:00:00 2001 From: Melissa Jost Date: Fri, 9 Dec 2022 16:17:25 -0800 Subject: [PATCH 44/45] tests: Remove get_runtime_isa() from parsec_disk_run.py This change removes the call to get_runtime_isa(), as it has been deprecated. Change-Id: Ie1b0b5fb456fd8ed504a531841fe4ea8e211502c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66611 Maintainer: Boris Shingarov Maintainer: Bobby Bruce Reviewed-by: Boris Shingarov Tested-by: kokoro --- tests/gem5/configs/parsec_disk_run.py | 5 ----- 1 file changed, 5 deletions(-) diff --git a/tests/gem5/configs/parsec_disk_run.py b/tests/gem5/configs/parsec_disk_run.py index 4275ffbd3f..fbe1cd3688 100644 --- a/tests/gem5/configs/parsec_disk_run.py +++ b/tests/gem5/configs/parsec_disk_run.py @@ -214,11 +214,6 @@ board.set_kernel_disk_workload( readfile_contents=command, ) -print("Running with ISA: " + get_runtime_isa().name) -print("Running with protocol: " + get_runtime_coherence_protocol().name) -print() - - # Here we define some custom workbegin/workend exit event generators. Here we # want to switch to detailed CPUs at the beginning of the ROI, then continue to # the end of of the ROI. Then we exit the simulation. From 61aabd516e84828004b15371baa8b9be794c06d4 Mon Sep 17 00:00:00 2001 From: "Bobby R. Bruce" Date: Fri, 2 Dec 2022 11:28:15 -0800 Subject: [PATCH 45/45] misc: Update RELEASE-NOTES.md for v22.1.0.0 Change-Id: I28753f24742ca156e19ac2af4fb302f9de20e852 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66391 Reviewed-by: Bobby Bruce Reviewed-by: Jason Lowe-Power Reviewed-by: Matthew Poremba Maintainer: Bobby Bruce Reviewed-by: Matt Sinclair Tested-by: kokoro Reviewed-by: Daniel Carvalho --- RELEASE-NOTES.md | 118 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 118 insertions(+) diff --git a/RELEASE-NOTES.md b/RELEASE-NOTES.md index 881285f695..c10cc40b12 100644 --- a/RELEASE-NOTES.md +++ b/RELEASE-NOTES.md @@ -1,3 +1,121 @@ +# Version 22.1.0.0 + +This release has 500 contributions from 48 unique contributors and marks our second major release of 2022. +This release incorporates several new features, improvements, and bug fixes for the computer architecture reserach community. + +See below for more details! + +## New features and improvements + +- The gem5 binary can now be compiled to include multiple ISA targets. +A compilation of gem5 which includes all gem5 ISAs can be created using: `scons build/ALL/gem5.opt`. +This will use the Ruby `MESI_Two_Level` cache coherence protocol by default, to use other protocols: `scons build/ALL/gem5.opt PROTOCOL=`. +The classic cache system may continue to be used regardless as to which Ruby cache coherence protocol is compiled. +- The `m5` Python module now includes functions to set exit events are particular simululation ticks: + - *setMaxTick(tick)* : Used to to specify the maximum simulation tick. + - *getMaxTick()* : Used to obtain the maximum simulation tick value. + - *getTicksUntilMax()*: Used to get the number of ticks remaining until the maximum tick is reached. + - *scheduleTickExitFromCurrent(tick)* : Used to schedule an exit exit event a specified number of ticks in the future. + - *scheduleTickExitAbsolute(tick)* : Used to schedule an exit event as a specified tick. +- We now include the `RiscvMatched` board as part of the gem5 stdlib. +This board is modeled after the [HiFive Unmatched board](https://www.sifive.com/boards/hifive-unmatched) and may be used to emulate its behavior. +See "configs/example/gem5_library/riscv-matched-fs.py" and "configs/example/gem5_library/riscv-matched-hello.py" for examples using this board. +- An API for [SimPoints](https://doi.org/10.1145/885651.781076) has been added. +SimPoints can substantially improve gem5 Simulation time by only simulating representative parts of a simulation then extrapolating statistical data accordingly. +Examples of using SimPoints with gem5 can be found in "configs/example/gem5_library/checkpoints/simpoints-se-checkpoint.py" and "configs/example/gem5_library/checkpoints/simpoints-se-restore.py". +- "Workloads" have been introduced to gem5. +Workloads have been incorporated into the gem5 Standard library. +They can be used specify the software to be run on a simulated system that come complete with input parameters and any other dependencies necessary to run a simuation on the target hardware. +At the level of the gem5 configuration script a user may specify a workload via a board's `set_workload` function. +For example, `set_workload(Workload("x86-ubuntu-18.04-boot"))` sets the board to use the "x86-ubuntu-18.04-boot" workload. +This workload specifies a boot consisting of the Linux 5.4.49 kernel then booting an Ubunutu 18.04 disk image, to exit upon booting. +Workloads are agnostic to underlying gem5 design and, via the gem5-resources infrastructure, will automatically retrieve all necessary kernels, disk-images, etc., necessary to execute. +Examples of using gem5 Workloads can be found in "configs/example/gem5_library/x86-ubuntu-ruby.py" and "configs/example/gem5_library/riscv-ubuntu-run.py". +- To aid gem5 developers, we have incorporated [pre-commit](https://pre-commit.com) checks into gem5. +These checks automatically enforce the gem5 style guide on Python files and a subset of other requirements (such as line length) on altered code prior to a `git commit`. +Users may install pre-commit by running `./util/pre-commit-install.sh`. +Passing these checks is a requirement to submit code to gem5 so installation is strongly advised. +- A multiprocessing module has been added. +This allows for multiple simulations to be run from a single gem5 execution via a single gem5 configuration script. +Example of usage found [in this commit message](https://gem5-review.googlesource.com/c/public/gem5/+/63432). +**Note: This feature is still in development. +While functional, it'll be subject to subtantial changes in future releases of gem5**. +- The stdlib's `ArmBoard` now supports Ruby caches. +- Due to numerious fixes and improvements, Ubuntu 22.04 can be booted as a gem5 workload, both in FS and SE mode. +- Substantial improvements have been made to gem5's GDB capabilities. +- The `HBM2Stack` has been added to the gem5 stdlib as a memory component. +- The `MinorCPU` has been fully incorporated into the gem5 Standard Library. +- We now allow for full-system simulation of GPU applications. +The introduction of GPU FS mode allows for the same use-cases as SE mode but reduces the requirement of specific host environments or usage of a Docker container. +The GPU FS mode also has improved simulated speed by functionally simulating memory copies, and provides an easier update path for gem5 developers. +An X86 host and KVM are required to run GPU FS mode. + +## API (user facing) changes + +- The default CPU Vendor String has been updated to `HygonGenuine`. +This is due to newer versions of GLIBC being more strict about checking current system's supported features. +The previous value, `M5 Simulator`, is not recognized as a valid vendor string and therefore GLIBC returns an error. +- [The stdlib's `_connect_things` funciton call has been moved from the `AbstractBoard`'s constructor to be run as board pre-instantiation process](https://gem5-review.googlesource.com/c/public/gem5/+/65051). +This is to overcome instances where stdlib components (memory, processor, and cache hierarhcy) require Board information known only after its construction. +**This change breaks cases where a user utilizes the stdlib `AbstractBoard` but does not use the stdlib `Simulator` module. This can be fixed by adding the `_pre_instantiate` function before `m5.instantiate`**. +An exception has been added which explains this fix, if this error occurs. +- The setting of checkpoints has been moved from the stdlib's "set_workload" functions to the `Simulator` module. +Setting of checkpoints via the stdlib's "set_workload" functions is now deprecated and will be removed in future releases of gem5. +- The gem5 namespace `Trace` has been renamed `trace` to conform to the gem5 style guide. +- Due to the allowing of multiple ISAs per gem5 build, the `TARGET_ISA` variable has been replaced with `USE_$(ISA)` variables. +For example, if a build contains both the X86 and ARM ISAs the `USE_X86` and `USE_ARM` variables will be set. + +## Big Fixes + +- Several compounding bugs were causing bugs with floating point operations within gem5 simulations. +These have been fixed. +- Certain emulated syscalls were behaving incorrectly when using RISC-V due to incorrect `open(2)` flag values. +These values have been fixed. +- The GIVv3 List register mapping has been fixed. +- Access permissions for GICv3 cpu registers have been fixed. +- In previous releases of gem5 the `sim_quantum` value was set for all cores when using the Standard Library. +This caused issues when setting exit events at a particular tick as it resulted in the exit being off by `sim_quantum`. +As such, the `sim_quantum` value is only when using KVM cores. +- PCI ranges in `VExpress_GEM5_Foundation` fixed. +- The `SwitchableProcessor` processor has been fixed to allow switching to a KVM core. +Previously the `SwitchableProcessor` only allowed a user to switch from a KVM core to a non-KVM core. +- The Standard Library has been fixed to permit multicore simulations in SE mode. +- [A bug was fixed in the rcr X86 instruction](https://gem5.atlassian.net/browse/GEM5-1265). + +## Build related changes + +- gem5 can now be compiled with Scons 4 build system. +- gem5 can now be compiled with Clang version 14 (minimum Clang version 6). +- gem5 can now be compiled with GCC Version 12 (minimum GCC version 7). + + +## Other minor updates + +- The gem5 stdlib examples in "configs/example/gem5_library" have been updated to, where appropriate, use the stdlib's Simulator module. +These example configurations can be used for reference as to how `Simulator` module may be utilized in gem5. +- Granulated SGPR computation has been added for gfx9 gpu-compute. +- The stdlib statistics have been improved: + - A `get_simstats` function has been added to access statistics from the `Simulator` module. + - Statistics can be printed: `print(simstats.board.core.some_integer)`. +- GDB ports are now specified for each workload, as opposed to per-simulation run. +- The `m5` utility has been expanded to include "workbegin" and "workend" annotations. +This can be added with `m5 workbegin` and `m5 workend`. +- A `PrivateL1SharedL2CacheHierarchy` has been added to the Standard Library. +- A `GEM5_USE_PROXY` environment variable has been added. +This allows users to specify a socks5 proxy server to use when obtaining gem5 resources and the resources.json file. +It uses the format `:`. +- The fastmodel support has been improved to function with Linux Kernel 5.x. +- The `set_se_binary_workload` function now allows for the passing of input parameters to a binary workload. +- A functional CHI cache hierarchy has been added to the gem5 Standard Library: "src/python/gem5/components/cachehierarchies/chi/private_l1_cache_hierarchy.py". +- The RISC-V K extension has been added. +It includes the following instructions: + - Zbkx: xperm8, xperm4 + - Zknd: aes64ds, aes64dsm, aes64im, aes64ks1i, aes64ks2 + - Zkne: aes64es, aes64esm, aes64ks1i, aes64ks2 + - Zknh: sha256sig0, sha256sig1, sha256sum0, sha256sum1, sha512sig0, sha512sig1, sha512sum0, sha512sum1 + - Zksed: sm4ed, sm4ks + - Zksh: sm3p0, sm3p1 + # Version 22.0.0.1 **[HOTFIX]** Fixes relative import in "src/python/gem5/components/processors/simple_core.py".