diff --git a/src/mem/Bus.py b/src/mem/Bus.py
index 05033d3824..12657e1777 100644
--- a/src/mem/Bus.py
+++ b/src/mem/Bus.py
@@ -49,7 +49,7 @@ class BaseBus(MemObject):
     master = VectorMasterPort("vector port for connecting slaves")
     clock = Param.Clock("1GHz", "bus clock speed")
     header_cycles = Param.Int(1, "cycles of overhead per transaction")
-    width = Param.Int(64, "bus width (bytes)")
+    width = Param.Int(8, "bus width (bytes)")
     block_size = Param.Int(64, "The default block size if not set by " \
                                "any connected module")