From 1bde42760f51e4fb6b54107ad3ac65be8427968c Mon Sep 17 00:00:00 2001
From: Roger Chang <rogerycchang@google.com>
Date: Mon, 4 Sep 2023 15:15:23 +0800
Subject: [PATCH] arch-riscv: Get vl, vtype and vlenb from PCState

Change-Id: I0ded57a3dc2db6fcc7121f147bcaf6d8a8873f6a
---
 src/arch/riscv/isa.cc | 15 +++++++++++++--
 1 file changed, 13 insertions(+), 2 deletions(-)

diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc
index 14d741e9e4..4cb5082cad 100644
--- a/src/arch/riscv/isa.cc
+++ b/src/arch/riscv/isa.cc
@@ -40,6 +40,7 @@
 #include "arch/riscv/mmu.hh"
 #include "arch/riscv/pagetable.hh"
 #include "arch/riscv/pmp.hh"
+#include "arch/riscv/pcstate.hh"
 #include "arch/riscv/regs/float.hh"
 #include "arch/riscv/regs/int.hh"
 #include "arch/riscv/regs/misc.hh"
@@ -503,9 +504,19 @@ ISA::readMiscReg(RegIndex idx)
         }
       case MISCREG_VLENB:
         {
-            return VLENB;
+            auto rpc = tc->pcState().as<PCState>();
+            return rpc.vlenb();
+        }
+      case MISCREG_VTYPE:
+        {
+            auto rpc = tc->pcState().as<PCState>();
+            return rpc.vtype();
+        }
+      case MISCREG_VL:
+        {
+            auto rpc = tc->pcState().as<PCState>();
+            return (RegVal)rpc.vl();
         }
-        break;
       case MISCREG_VCSR:
         {
             return readMiscRegNoEffect(MISCREG_VXSAT) &