diff --git a/src/arch/arm/mmapped_ipr.hh b/src/arch/arm/mmapped_ipr.hh
index d515b83717..1cccdbd79e 100644
--- a/src/arch/arm/mmapped_ipr.hh
+++ b/src/arch/arm/mmapped_ipr.hh
@@ -39,14 +39,44 @@
  * ISA-specific helper functions for memory mapped IPR accesses.
  */
 
-#include "arch/generic/mmapped_ipr.hh"
+#include "base/types.hh"
+#include "mem/packet.hh"
+#include "mem/packet_access.hh"
+#include "sim/pseudo_inst.hh"
+#include "sim/system.hh"
 
 class ThreadContext;
 
 namespace ArmISA
 {
-    using GenericISA::handleIprRead;
-    using GenericISA::handleIprWrite;
+
+inline Cycles
+handleIprRead(ThreadContext *tc, Packet *pkt)
+{
+    Addr addr = pkt->getAddr();
+    auto m5opRange = tc->getSystemPtr()->m5opRange();
+    if (m5opRange.contains(addr)) {
+        uint8_t func;
+        PseudoInst::decodeAddrOffset(addr - m5opRange.start(), func);
+        uint64_t ret = PseudoInst::pseudoInst<PseudoInstABI>(tc, func);
+        pkt->setLE(ret);
+    }
+    return Cycles(1);
+}
+
+inline Cycles
+handleIprWrite(ThreadContext *tc, Packet *pkt)
+{
+    Addr addr = pkt->getAddr();
+    auto m5opRange = tc->getSystemPtr()->m5opRange();
+    if (m5opRange.contains(addr)) {
+        uint8_t func;
+        PseudoInst::decodeAddrOffset(addr - m5opRange.start(), func);
+        PseudoInst::pseudoInst<PseudoInstABI>(tc, func);
+    }
+    return Cycles(1);
+}
+
 } // namespace ArmISA
 
 #endif
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index 5ecd7a45c8..5358159fbc 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -138,12 +138,8 @@ TLB::finalizePhysical(const RequestPtr &req,
 {
     const Addr paddr = req->getPaddr();
 
-    if (m5opRange.contains(paddr)) {
-        req->setFlags(Request::MMAPPED_IPR | Request::GENERIC_IPR);
-        req->setPaddr(GenericISA::iprAddressPseudoInst(
-                          (paddr >> 8) & 0xFF,
-                          paddr & 0xFF));
-    }
+    if (m5opRange.contains(paddr))
+        req->setFlags(Request::MMAPPED_IPR);
 
     return NoFault;
 }