From 1bc23ca966e5ad426a794bf8c3d2af44a3c80677 Mon Sep 17 00:00:00 2001
From: Matthew Poremba <matthew.poremba@amd.com>
Date: Fri, 4 Feb 2022 14:38:30 -0600
Subject: [PATCH] mem-ruby: Add protocol prints to MOESI_AMD_BASE-dma

Change-Id: I59ed7311a8dc2a06ce1df0027891ba8e24e8a89e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/56447
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
---
 src/mem/ruby/protocol/MOESI_AMD_Base-dma.sm | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/mem/ruby/protocol/MOESI_AMD_Base-dma.sm b/src/mem/ruby/protocol/MOESI_AMD_Base-dma.sm
index dbecabd1cc..993387dcd0 100644
--- a/src/mem/ruby/protocol/MOESI_AMD_Base-dma.sm
+++ b/src/mem/ruby/protocol/MOESI_AMD_Base-dma.sm
@@ -139,6 +139,7 @@ machine(MachineType:DMA, "DMA Controller")
         out_msg.Len := in_msg.Len;
         out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory));
         out_msg.MessageSize := MessageSizeType:Writeback_Control;
+        DPRINTF(ProtocolTrace, "%s\n", out_msg);
       }
     }
   }
@@ -154,6 +155,7 @@ machine(MachineType:DMA, "DMA Controller")
           out_msg.Len := in_msg.Len;
           out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory));
           out_msg.MessageSize := MessageSizeType:Writeback_Control;
+          DPRINTF(ProtocolTrace, "%s\n", out_msg);
         }
       }
   }