arch-riscv: Add support for RISC-V semihosting (#681)

See https://github.com/riscv-software-src/riscv-semihosting for the
current specification. Almost all code is shared with the Arm
implementation.

Tested by running some binaries built with
[picolibc](https://github.com/picolibc/picolibc).

src/sim/workload.hh

@@ -103,6 +103,8 @@ class Workload : public SimObject
     virtual Addr getEntry() const = 0;
     virtual ByteOrder byteOrder() const = 0;
     virtual loader::Arch getArch() const = 0;
+    /// Returns the semihosting interface if supported by the current workload.
+    virtual SimObject* getSemihosting() const { return nullptr; }
 
     virtual const loader::SymbolTable &symtab(ThreadContext *tc) = 0;
     virtual bool insertSymbol(const loader::Symbol &symbol) = 0;