From 19628e746d0bbd8fef10dc1e610be81de194fcf4 Mon Sep 17 00:00:00 2001
From: Giacomo Travaglini <giacomo.travaglini@arm.com>
Date: Fri, 26 Jan 2024 15:41:02 +0000
Subject: [PATCH] arch-arm: Add readRegister/writeRegister templates

This is adding two templated functions for reading/writing
system registers (MiscRegs). It is introducing them inside
a new misc_regs namespace.

Change-Id: I21233337c057673d46d1147971ebabbfc2c2bb6a
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
---
 src/arch/arm/regs/misc_accessors.hh | 96 +++++++++++++++++++++++++++++
 1 file changed, 96 insertions(+)
 create mode 100644 src/arch/arm/regs/misc_accessors.hh

diff --git a/src/arch/arm/regs/misc_accessors.hh b/src/arch/arm/regs/misc_accessors.hh
new file mode 100644
index 0000000000..bce95120e3
--- /dev/null
+++ b/src/arch/arm/regs/misc_accessors.hh
@@ -0,0 +1,96 @@
+/*
+ * Copyright (c) 2024 Arm Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __ARCH_ARM_REGS_MISC_ACCESSORS_HH__
+#define __ARCH_ARM_REGS_MISC_ACCESSORS_HH__
+
+#include "arch/arm/regs/misc_types.hh"
+#include "cpu/thread_context.hh"
+
+namespace gem5
+{
+
+namespace ArmISA
+{
+
+namespace misc_regs
+{
+
+template <typename RegAccessor>
+MiscRegIndex
+getRegVersion(ExceptionLevel el)
+{
+    switch (el) {
+      case EL0:
+        return RegAccessor::el0;
+      case EL1:
+        return RegAccessor::el1;
+      case EL2:
+        return RegAccessor::el2;
+      case EL3:
+        return RegAccessor::el3;
+      default:
+        panic("Invalid EL\n");
+    }
+}
+
+template <typename RegAccessor>
+typename RegAccessor::type
+readRegister(ThreadContext *tc, ExceptionLevel el)
+{
+    return tc->readMiscReg(getRegVersion<RegAccessor>(el));
+}
+
+template <typename RegAccessor>
+typename RegAccessor::type
+readRegisterNoEffect(ThreadContext *tc, ExceptionLevel el)
+{
+    return tc->readMiscRegNoEffect(getRegVersion<RegAccessor>(el));
+}
+
+template <typename RegAccessor>
+void
+writeRegister(ThreadContext *tc, RegVal val, ExceptionLevel el)
+{
+    tc->setMiscReg(getRegVersion<RegAccessor>(el), val);
+}
+
+} // namespace misc_regs
+} // namespace ArmISA
+} // namespace gem5
+
+#endif // __ARCH_ARM_REGS_MISC_ACCESSORS_HH__