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misc: Revert "arch,cpu,mem,sim: Fold arch/locked_mem.hh..."

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This reverts commit a3f85217ab,
https://gem5-review.googlesource.com/c/public/gem5/+/48384

The reason for reverting this commit is it causes the Nightly build to
timeout: https://www.mail-archive.com/gem5-dev@gem5.org/msg40344.html

The exact cause of this failure was a stalling with the O3 processor on
ARM. The simulation reaches the following error and repeats until
timeout:

```
build/ARM/arch/arm/isa.cc:2634: warn: context 0: 2136500000 consecutive store conditional failures
```

The "realview-o3-ARM-x86_64-opt" test can replicate this:

```
./main.py run -j8 --uid
SuiteUID:tests/gem5/fs/linux/arm/test.py:realview-o3-ARM-x86_64-opt
```

Change-Id: I9e9a20753c2a25c143e6a73f58716feb41861cde
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49927
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Bobby R. Bruce
2021-09-03 10:31:34 -07:00
committed by Jason Lowe-Power
parent 737cdd7397
commit 1853d57dc3
23 changed files with 840 additions and 244 deletions
Download Patch File Download Diff File Expand all files Collapse all files

18
src/cpu/simple/atomic.cc
View File

@@ -41,6 +41,7 @@
#include "cpu/simple/atomic.hh"
#include "arch/locked_mem.hh"
#include "base/output.hh"
#include "config/the_isa.hh"
#include "cpu/exetrace.hh"
@@ -132,8 +133,8 @@ AtomicSimpleCPU::threadSnoop(PacketPtr pkt, ThreadID sender)
wakeup(tid);
}
threadInfo[tid]->thread->getIsaPtr()->handleLockedSnoop(pkt,
dcachePort.cacheBlockMask);
TheISA::handleLockedSnoop(threadInfo[tid]->thread,
pkt, dcachePort.cacheBlockMask);
}
}
}
@@ -297,8 +298,7 @@ AtomicSimpleCPU::AtomicCPUDPort::recvAtomicSnoop(PacketPtr pkt)
DPRINTF(SimpleCPU, "received invalidation for addr:%#x\n",
pkt->getAddr());
for (auto &t_info : cpu->threadInfo) {
t_info->thread->getIsaPtr()->handleLockedSnoop(pkt,
cacheBlockMask);
TheISA::handleLockedSnoop(t_info->thread, pkt, cacheBlockMask);
}
}
@@ -324,8 +324,7 @@ AtomicSimpleCPU::AtomicCPUDPort::recvFunctionalSnoop(PacketPtr pkt)
DPRINTF(SimpleCPU, "received invalidation for addr:%#x\n",
pkt->getAddr());
for (auto &t_info : cpu->threadInfo) {
t_info->thread->getIsaPtr()->handleLockedSnoop(pkt,
cacheBlockMask);
TheISA::handleLockedSnoop(t_info->thread, pkt, cacheBlockMask);
}
}
}
@@ -408,7 +407,7 @@ AtomicSimpleCPU::readMem(Addr addr, uint8_t *data, unsigned size,
assert(!pkt.isError());
if (req->isLLSC()) {
thread->getIsaPtr()->handleLockedRead(req);
TheISA::handleLockedRead(thread, req);
}
}
@@ -483,8 +482,9 @@ AtomicSimpleCPU::writeMem(uint8_t *data, unsigned size, Addr addr,
if (req->isLLSC()) {
assert(curr_frag_id == 0);
do_access = thread->getIsaPtr()->handleLockedWrite(req,
dcachePort.cacheBlockMask);
do_access =
TheISA::handleLockedWrite(thread, req,
dcachePort.cacheBlockMask);
} else if (req->isSwap()) {
assert(curr_frag_id == 0);
if (req->isCondSwap()) {

11
src/cpu/simple/timing.cc
View File

@@ -41,6 +41,7 @@
#include "cpu/simple/timing.hh"
#include "arch/locked_mem.hh"
#include "base/compiler.hh"
#include "config/the_isa.hh"
#include "cpu/exetrace.hh"
@@ -275,7 +276,7 @@ TimingSimpleCPU::handleReadPacket(PacketPtr pkt)
// We're about the issues a locked load, so tell the monitor
// to start caring about this address
if (pkt->isRead() && pkt->req->isLLSC()) {
thread->getIsaPtr()->handleLockedRead(pkt->req);
TheISA::handleLockedRead(thread, pkt->req);
}
if (req->isLocalAccess()) {
Cycles delay = req->localAccessor(thread->getTC(), pkt);
@@ -324,8 +325,7 @@ TimingSimpleCPU::sendData(const RequestPtr &req, uint8_t *data, uint64_t *res,
bool do_access = true; // flag to suppress cache access
if (req->isLLSC()) {
do_access = thread->getIsaPtr()->handleLockedWrite(
req, dcachePort.cacheBlockMask);
do_access = TheISA::handleLockedWrite(thread, req, dcachePort.cacheBlockMask);
} else if (req->isCondSwap()) {
assert(res);
req->setExtraData(*res);
@@ -641,7 +641,7 @@ TimingSimpleCPU::threadSnoop(PacketPtr pkt, ThreadID sender)
if (getCpuAddrMonitor(tid)->doMonitor(pkt)) {
wakeup(tid);
}
threadInfo[tid]->thread->getIsaPtr()->handleLockedSnoop(pkt,
TheISA::handleLockedSnoop(threadInfo[tid]->thread, pkt,
dcachePort.cacheBlockMask);
}
}
@@ -1100,8 +1100,7 @@ TimingSimpleCPU::DcachePort::recvTimingSnoopReq(PacketPtr pkt)
// It is not necessary to wake up the processor on all incoming packets
if (pkt->isInvalidate() || pkt->isWrite()) {
for (auto &t_info : cpu->threadInfo) {
t_info->thread->getIsaPtr()->handleLockedSnoop(pkt,
cacheBlockMask);
TheISA::handleLockedSnoop(t_info->thread, pkt, cacheBlockMask);
}
}
}