arm: Raise an alignment fault if a PC has illegal alignment

We currently don't handle unaligned PCs correctly. There is one check
for unaligned PCs in the TLB when running in aarch64 mode, but this
check does not cover cases where the CPU does not do a TLB lookup when
decoding an instruction (e.g., a branch stays within the same cache
line). Additionally, the Decoder class sometimes throws an assertion
for unaligned PCs which breaks speculation.

This changeset introduces a decoder fault bit field in the ExtMachInst
structure. This field can be used to signal a decoder failure. If set,
the decoder generates an internal gem5fault instruction instead of a
normal instruction. This instruction in turns either panics (fault
type PANIC), returns an PCAlignmentFault (fault type UNALIGNED,
aarch64) or PrefetchAbort (fault type UNALIGNED, aarch32).

The patch causes minor changes to the realview64 regressions, and a
stats bump will follow.

src/arch/arm/SConscript

@@ -57,6 +57,7 @@ if env['TARGET_ISA'] == 'arm':
     Source('insts/misc.cc')
     Source('insts/misc64.cc')
     Source('insts/pred_inst.cc')
+    Source('insts/pseudo.cc')
     Source('insts/static_inst.cc')
     Source('insts/vfp.cc')
     Source('insts/fplib.cc')

src/arch/arm/decoder.cc

@@ -139,7 +139,7 @@ void
 Decoder::consumeBytes(int numBytes)
 {
     offset += numBytes;
-    assert(offset <= sizeof(MachInst));
+    assert(offset <= sizeof(MachInst) || emi.decoderFault);
     if (offset == sizeof(MachInst))
         outOfBytes = true;
 }
@@ -154,6 +154,10 @@ Decoder::moreBytes(const PCState &pc, Addr fetchPC, MachInst inst)
     emi.fpscrLen = fpscrLen;
     emi.fpscrStride = fpscrStride;
 
+    const Addr alignment(pc.thumb() ? 0x1 : 0x3);
+    emi.decoderFault = static_cast<uint8_t>(
+        pc.instAddr() & alignment ? DecoderFault::UNALIGNED : DecoderFault::OK);
+
     outOfBytes = false;
     process();
 }

src/arch/arm/insts/pseudo.cc

@@ -0,0 +1,101 @@
+/*
+ * Copyright (c) 2014 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Andreas Sandberg
+ */
+
+#include "arch/arm/insts/pseudo.hh"
+#include "cpu/exec_context.hh"
+
+DecoderFaultInst::DecoderFaultInst(ExtMachInst _machInst)
+    : ArmStaticInst("gem5decoderFault", _machInst, No_OpClass),
+      faultId(static_cast<DecoderFault>(
+                  static_cast<uint8_t>(_machInst.decoderFault)))
+{
+    // Don't call execute() if we're on a speculative path and the
+    // fault is an internal panic fault.
+    flags[IsNonSpeculative] = (faultId == DecoderFault::PANIC);
+}
+
+Fault
+DecoderFaultInst::execute(ExecContext *xc, Trace::InstRecord *traceData) const
+{
+    const PCState pc_state(xc->pcState());
+    const Addr pc(pc_state.instAddr());
+
+    switch (faultId) {
+      case DecoderFault::UNALIGNED:
+        if (machInst.aarch64) {
+            return std::make_shared<PCAlignmentFault>(pc);
+        } else {
+            // TODO: We should check if we the receiving end is in
+            // aarch64 mode and raise a PCAlignment fault instead.
+            return std::make_shared<PrefetchAbort>(
+                pc, ArmFault::AlignmentFault);
+        }
+
+      case DecoderFault::PANIC:
+        panic("Internal error in instruction decoder\n");
+
+      case DecoderFault::OK:
+        panic("Decoder fault instruction without decoder fault.\n");
+    }
+
+    panic("Unhandled fault type");
+}
+
+const char *
+DecoderFaultInst::faultName() const
+{
+    switch (faultId) {
+      case DecoderFault::OK:
+        return "OK";
+
+      case DecoderFault::UNALIGNED:
+        return "UnalignedInstruction";
+
+      case DecoderFault::PANIC:
+        return "DecoderPanic";
+    }
+
+    panic("Unhandled fault type");
+}
+
+std::string
+DecoderFaultInst::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+    return csprintf("gem5fault %s", faultName());
+}

src/arch/arm/insts/pseudo.hh

@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2014 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Andreas Sandberg
+ */
+
+#ifndef __ARCH_ARM_INSTS_PSEUDO_HH__
+#define __ARCH_ARM_INSTS_PSEUDO_HH__
+
+#include "arch/arm/insts/static_inst.hh"
+
+class DecoderFaultInst : public ArmStaticInst
+{
+  protected:
+    DecoderFault faultId;
+
+    const char *faultName() const;
+
+  public:
+    DecoderFaultInst(ExtMachInst _machInst);
+
+    Fault execute(ExecContext *xc, Trace::InstRecord *traceData) const;
+
+    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+};
+
+
+#endif

src/arch/arm/isa/bitfields.isa

@@ -46,6 +46,8 @@
 //
 
 // Opcode fields
+def bitfield DECODERFAULT  decoderFault;
+
 def bitfield ENCODING      encoding;
 def bitfield OPCODE        opcode;
 def bitfield MEDIA_OPCODE  mediaOpcode;

src/arch/arm/isa/decoder/decoder.isa

@@ -40,13 +40,15 @@
 //
 // Authors: Gabe Black
 
-decode THUMB default Unknown::unknown() {
-0: decode AARCH64 {
-    0:
-    ##include "arm.isa"
-    1:
-    ##include "aarch64.isa"
-}
-1:
-##include "thumb.isa"
+decode DECODERFAULT default DecoderFault::decoderFault() {
+    0: decode THUMB default Unknown::unknown() {
+        0: decode AARCH64 {
+            0:
+            ##include "arm.isa"
+            1:
+            ##include "aarch64.isa"
+        }
+        1:
+        ##include "thumb.isa"
+    }
 }

src/arch/arm/isa/formats/formats.isa

@@ -88,3 +88,6 @@
 
 //M5 Psuedo-ops
 ##include "m5ops.isa"
+
+//gem5-internal pseudo instructions
+##include "pseudo.isa"

src/arch/arm/isa/formats/pseudo.isa

@@ -0,0 +1,44 @@
+// -*- mode:c++ -*-
+
+// Copyright (c) 2014 ARM Limited
+// All rights reserved
+//
+// The license below extends only to copyright in the software and shall
+// not be construed as granting a license to any other intellectual
+// property including but not limited to intellectual property relating
+// to a hardware implementation of the functionality of the software
+// licensed hereunder.  You may use the software subject to the license
+// terms below provided that you ensure that this notice is replicated
+// unmodified and in its entirety in all distributions of the software,
+// modified or unmodified, in source code or in binary form.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Andreas Sandberg
+
+def format DecoderFault() {{
+    decode_block = '''
+        return new DecoderFaultInst(machInst);
+    '''
+}};

src/arch/arm/isa/includes.isa

@@ -61,6 +61,7 @@ output header {{
 #include "arch/arm/insts/mult.hh"
 #include "arch/arm/insts/neon64_mem.hh"
 #include "arch/arm/insts/pred_inst.hh"
+#include "arch/arm/insts/pseudo.hh"
 #include "arch/arm/insts/static_inst.hh"
 #include "arch/arm/insts/vfp.hh"
 #include "arch/arm/isa_traits.hh"

src/arch/arm/tlb.cc

@@ -982,11 +982,6 @@ TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
                  "flags %#x tranType 0x%x\n", vaddr_tainted, mode, isStage2,
                  scr, sctlr, flags, tranType);
 
-    // Generate an alignment fault for unaligned PC
-    if (aarch64 && is_fetch && (req->getPC() & mask(2))) {
-        return std::make_shared<PCAlignmentFault>(req->getPC());
-    }
-
     // If this is a clrex instruction, provide a PA of 0 with no fault
     // This will force the monitor to set the tracked address to 0
     // a bit of a hack but this effectively clrears this processors monitor

src/arch/arm/types.hh

@@ -68,8 +68,10 @@ namespace ArmISA
         Bitfield<1, 0> bottom2;
     EndBitUnion(ITSTATE)
 
-
     BitUnion64(ExtMachInst)
+        // Decoder state
+        Bitfield<63, 62> decoderFault; // See DecoderFault
+
         // ITSTATE bits
         Bitfield<55, 48> itstate;
         Bitfield<55, 52> itstateCond;
@@ -626,6 +628,16 @@ namespace ArmISA
         EC_SERROR                  = 0x2F
     };
 
+    /**
+     * Instruction decoder fault codes in ExtMachInst.
+     */
+    enum DecoderFault : std::uint8_t {
+        OK = 0x0, ///< No fault
+        UNALIGNED = 0x1, ///< Unaligned instruction fault
+
+        PANIC = 0x3, ///< Internal gem5 error
+    };
+
     BitUnion8(OperatingMode64)
         Bitfield<0> spX;
         Bitfield<3, 2> el;