diff --git a/components_library/cachehierarchies/classic/caches/l1dcache.py b/components_library/cachehierarchies/classic/caches/l1dcache.py
index 207692f8de..2f83905992 100644
--- a/components_library/cachehierarchies/classic/caches/l1dcache.py
+++ b/components_library/cachehierarchies/classic/caches/l1dcache.py
@@ -28,7 +28,7 @@ from ....utils.override import *
 
 from m5.objects import Cache, BasePrefetcher, StridePrefetcher
 
-from typing import Optional
+from typing import Optional, Type
 
 
 class L1DCache(Cache):
@@ -46,7 +46,7 @@ class L1DCache(Cache):
         mshrs: Optional[int] = 16,
         tgts_per_mshr: Optional[int] = 20,
         writeback_clean: Optional[bool] = True,
-        prefetcher: BasePrefetcher = StridePrefetcher(),
+        PrefetcherCls: Type[BasePrefetcher] = StridePrefetcher,
     ):
         super(L1DCache, self).__init__()
         self.size = size
@@ -57,4 +57,4 @@ class L1DCache(Cache):
         self.mshrs = mshrs
         self.tgts_per_mshr = tgts_per_mshr
         self.writeback_clean = writeback_clean
-        self.prefetcher = prefetcher
+        self.prefetcher = PrefetcherCls()
diff --git a/components_library/cachehierarchies/classic/caches/l1icache.py b/components_library/cachehierarchies/classic/caches/l1icache.py
index 960b6dcc9a..214de416cd 100644
--- a/components_library/cachehierarchies/classic/caches/l1icache.py
+++ b/components_library/cachehierarchies/classic/caches/l1icache.py
@@ -24,7 +24,7 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from typing import Optional
+from typing import Optional, Type
 
 from m5.objects import Cache, BasePrefetcher, StridePrefetcher
 
@@ -46,7 +46,7 @@ class L1ICache(Cache):
         mshrs: Optional[int] = 16,
         tgts_per_mshr: Optional[int] = 20,
         writeback_clean: Optional[bool] = True,
-        prefetcher: BasePrefetcher = StridePrefetcher(),
+        PrefetcherCls: Type[BasePrefetcher] = StridePrefetcher,
     ):
         super(L1ICache, self).__init__()
         self.size = size
@@ -57,4 +57,4 @@ class L1ICache(Cache):
         self.mshrs = mshrs
         self.tgts_per_mshr = tgts_per_mshr
         self.writeback_clean = writeback_clean
-        self.prefetcher = prefetcher
+        self.prefetcher = PrefetcherCls()
diff --git a/components_library/cachehierarchies/classic/caches/l2cache.py b/components_library/cachehierarchies/classic/caches/l2cache.py
index 24370886ec..bd48919ac1 100644
--- a/components_library/cachehierarchies/classic/caches/l2cache.py
+++ b/components_library/cachehierarchies/classic/caches/l2cache.py
@@ -28,7 +28,7 @@ from ....utils.override import *
 
 from m5.objects import Cache, BasePrefetcher, StridePrefetcher
 
-from typing import Optional
+from typing import Optional, Type
 
 
 class L2Cache(Cache):
@@ -46,7 +46,7 @@ class L2Cache(Cache):
         mshrs: Optional[int] = 20,
         tgts_per_mshr: Optional[int] = 12,
         writeback_clean: Optional[bool] = True,
-        prefetcher: BasePrefetcher = StridePrefetcher(),
+        PrefetcherCls: Type[BasePrefetcher] = StridePrefetcher,
     ):
         super(L2Cache, self).__init__()
         self.size = size
@@ -57,4 +57,4 @@ class L2Cache(Cache):
         self.mshrs = mshrs
         self.tgts_per_mshr = tgts_per_mshr
         self.writeback_clean = writeback_clean
-        self.prefetcher = prefetcher
+        self.prefetcher = PrefetcherCls()