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Ruby: Remove CacheMsg class from SLICC

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The goal of the patch is to do away with the CacheMsg class currently in use
in coherence protocols. In place of CacheMsg, the RubyRequest class will used.
This class is already present in slicc_interface/RubyRequest.hh. In fact,
objects of class CacheMsg are generated by copying values from a RubyRequest
object.
This commit is contained in:
Nilay Vaish
2011-03-22 06:41:54 -05:00
parent 46cce440be
commit 1764ebbf30
23 changed files with 208 additions and 166 deletions
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12
src/mem/protocol/MESI_CMP_directory-L1cache.sm
View File

@@ -267,9 +267,9 @@ machine(L1Cache, "MSI Directory L1 Cache CMP")
}
// Mandatory Queue betweens Node's CPU and it's L1 caches
in_port(mandatoryQueue_in, CacheMsg, mandatoryQueue, desc="...") {
in_port(mandatoryQueue_in, RubyRequest, mandatoryQueue, desc="...") {
if (mandatoryQueue_in.isReady()) {
peek(mandatoryQueue_in, CacheMsg, block_on="LineAddress") {
peek(mandatoryQueue_in, RubyRequest, block_on="LineAddress") {
// Check for data access to blocks in I-cache and ifetchs to blocks in D-cache
@@ -338,7 +338,7 @@ machine(L1Cache, "MSI Directory L1 Cache CMP")
// ACTIONS
action(a_issueGETS, "a", desc="Issue GETS") {
peek(mandatoryQueue_in, CacheMsg) {
peek(mandatoryQueue_in, RubyRequest) {
enqueue(requestIntraChipL1Network_out, RequestMsg, latency=l1_request_latency) {
out_msg.Address := address;
out_msg.Type := CoherenceRequestType:GETS;
@@ -355,7 +355,7 @@ machine(L1Cache, "MSI Directory L1 Cache CMP")
}
action(ai_issueGETINSTR, "ai", desc="Issue GETINSTR") {
peek(mandatoryQueue_in, CacheMsg) {
peek(mandatoryQueue_in, RubyRequest) {
enqueue(requestIntraChipL1Network_out, RequestMsg, latency=l1_request_latency) {
out_msg.Address := address;
out_msg.Type := CoherenceRequestType:GET_INSTR;
@@ -373,7 +373,7 @@ machine(L1Cache, "MSI Directory L1 Cache CMP")
action(b_issueGETX, "b", desc="Issue GETX") {
peek(mandatoryQueue_in, CacheMsg) {
peek(mandatoryQueue_in, RubyRequest) {
enqueue(requestIntraChipL1Network_out, RequestMsg, latency=l1_request_latency) {
out_msg.Address := address;
out_msg.Type := CoherenceRequestType:GETX;
@@ -391,7 +391,7 @@ machine(L1Cache, "MSI Directory L1 Cache CMP")
}
action(c_issueUPGRADE, "c", desc="Issue GETX") {
peek(mandatoryQueue_in, CacheMsg) {
peek(mandatoryQueue_in, RubyRequest) {
enqueue(requestIntraChipL1Network_out, RequestMsg, latency= l1_request_latency) {
out_msg.Address := address;
out_msg.Type := CoherenceRequestType:UPGRADE;

6
src/mem/protocol/MI_example-cache.sm
View File

@@ -181,9 +181,9 @@ machine(L1Cache, "MI Example L1 Cache")
}
// Mandatory Queue
in_port(mandatoryQueue_in, CacheMsg, mandatoryQueue, desc="...") {
in_port(mandatoryQueue_in, RubyRequest, mandatoryQueue, desc="...") {
if (mandatoryQueue_in.isReady()) {
peek(mandatoryQueue_in, CacheMsg, block_on="LineAddress") {
peek(mandatoryQueue_in, RubyRequest, block_on="LineAddress") {
Entry cache_entry := getCacheEntry(in_msg.LineAddress);
if (is_invalid(cache_entry) &&
@@ -281,7 +281,7 @@ machine(L1Cache, "MI Example L1 Cache")
}
action(p_profileMiss, "p", desc="Profile cache miss") {
peek(mandatoryQueue_in, CacheMsg) {
peek(mandatoryQueue_in, RubyRequest) {
cacheMemory.profileMiss(in_msg);
}
}

10
src/mem/protocol/MOESI_CMP_directory-L1cache.sm
View File

@@ -303,9 +303,9 @@ machine(L1Cache, "Directory protocol")
// Nothing from the unblock network
// Mandatory Queue betweens Node's CPU and it's L1 caches
in_port(mandatoryQueue_in, CacheMsg, mandatoryQueue, desc="...") {
in_port(mandatoryQueue_in, RubyRequest, mandatoryQueue, desc="...") {
if (mandatoryQueue_in.isReady()) {
peek(mandatoryQueue_in, CacheMsg, block_on="LineAddress") {
peek(mandatoryQueue_in, RubyRequest, block_on="LineAddress") {
// Check for data access to blocks in I-cache and ifetchs to blocks in D-cache
@@ -380,7 +380,7 @@ machine(L1Cache, "Directory protocol")
// ACTIONS
action(a_issueGETS, "a", desc="Issue GETS") {
peek(mandatoryQueue_in, CacheMsg) {
peek(mandatoryQueue_in, RubyRequest) {
enqueue(requestNetwork_out, RequestMsg, latency= request_latency) {
out_msg.Address := address;
out_msg.Type := CoherenceRequestType:GETS;
@@ -396,7 +396,7 @@ machine(L1Cache, "Directory protocol")
}
action(b_issueGETX, "b", desc="Issue GETX") {
peek(mandatoryQueue_in, CacheMsg) {
peek(mandatoryQueue_in, RubyRequest) {
enqueue(requestNetwork_out, RequestMsg, latency=request_latency) {
out_msg.Address := address;
out_msg.Type := CoherenceRequestType:GETX;
@@ -820,7 +820,7 @@ machine(L1Cache, "Directory protocol")
action(uu_profileMiss, "\u", desc="Profile the demand miss") {
peek(mandatoryQueue_in, CacheMsg) {
peek(mandatoryQueue_in, RubyRequest) {
// profile_miss(in_msg);
}
}

12
src/mem/protocol/MOESI_CMP_token-L1cache.sm
View File

@@ -622,9 +622,9 @@ machine(L1Cache, "Token protocol")
}
// Mandatory Queue
in_port(mandatoryQueue_in, CacheMsg, mandatoryQueue, desc="...", rank=0) {
in_port(mandatoryQueue_in, RubyRequest, mandatoryQueue, desc="...", rank=0) {
if (mandatoryQueue_in.isReady()) {
peek(mandatoryQueue_in, CacheMsg, block_on="LineAddress") {
peek(mandatoryQueue_in, RubyRequest, block_on="LineAddress") {
// Check for data access to blocks in I-cache and ifetchs to blocks in D-cache
TBE tbe := L1_TBEs[in_msg.LineAddress];
@@ -1310,7 +1310,7 @@ machine(L1Cache, "Token protocol")
L1_TBEs.allocate(address);
set_tbe(L1_TBEs[address]);
tbe.IssueCount := 0;
peek(mandatoryQueue_in, CacheMsg) {
peek(mandatoryQueue_in, RubyRequest) {
tbe.PC := in_msg.ProgramCounter;
tbe.AccessType := cache_request_type_to_access_type(in_msg.Type);
if (in_msg.Type == RubyRequestType:ATOMIC) {
@@ -1323,7 +1323,7 @@ machine(L1Cache, "Token protocol")
}
action(ta_traceStalledAddress, "ta", desc="Trace Stalled Address") {
peek(mandatoryQueue_in, CacheMsg) {
peek(mandatoryQueue_in, RubyRequest) {
APPEND_TRANSITION_COMMENT(in_msg.LineAddress);
}
}
@@ -1499,7 +1499,7 @@ machine(L1Cache, "Token protocol")
}
action(uu_profileMiss, "\u", desc="Profile the demand miss") {
peek(mandatoryQueue_in, CacheMsg) {
peek(mandatoryQueue_in, RubyRequest) {
if (L1DcacheMemory.isTagPresent(address)) {
L1DcacheMemory.profileMiss(in_msg);
} else {
@@ -1516,7 +1516,7 @@ machine(L1Cache, "Token protocol")
}
action(zz_stallAndWaitMandatoryQueue, "\z", desc="Send the head of the mandatory queue to the back of the queue.") {
peek(mandatoryQueue_in, CacheMsg) {
peek(mandatoryQueue_in, RubyRequest) {
APPEND_TRANSITION_COMMENT(in_msg.LineAddress);
}
stall_and_wait(mandatoryQueue_in, address);

8
src/mem/protocol/MOESI_hammer-cache.sm
View File

@@ -352,9 +352,9 @@ machine(L1Cache, "AMD Hammer-like protocol")
// Nothing from the request network
// Mandatory Queue
in_port(mandatoryQueue_in, CacheMsg, mandatoryQueue, desc="...", rank=0) {
in_port(mandatoryQueue_in, RubyRequest, mandatoryQueue, desc="...", rank=0) {
if (mandatoryQueue_in.isReady()) {
peek(mandatoryQueue_in, CacheMsg, block_on="LineAddress") {
peek(mandatoryQueue_in, RubyRequest, block_on="LineAddress") {
// Check for data access to blocks in I-cache and ifetchs to blocks in D-cache
TBE tbe := TBEs[in_msg.LineAddress];
@@ -695,7 +695,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
action(hh_store_hit, "\h", desc="Notify sequencer that store completed.") {
assert(is_valid(cache_entry));
DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
peek(mandatoryQueue_in, CacheMsg) {
peek(mandatoryQueue_in, RubyRequest) {
sequencer.writeCallback(address, testAndClearLocalHit(cache_entry),
cache_entry.DataBlk);
@@ -1022,7 +1022,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
}
action(uu_profileMiss, "\u", desc="Profile the demand miss") {
peek(mandatoryQueue_in, CacheMsg) {
peek(mandatoryQueue_in, RubyRequest) {
if (L1IcacheMemory.isTagPresent(address)) {
L1IcacheMemory.profileMiss(in_msg);
} else if (L1DcacheMemory.isTagPresent(address)) {

4
src/mem/protocol/Network_test-cache.sm
View File

@@ -132,9 +132,9 @@ machine(L1Cache, "Network_test L1 Cache")
out_port(responseNetwork_out, RequestMsg, responseFromCache);
// Mandatory Queue
in_port(mandatoryQueue_in, CacheMsg, mandatoryQueue, desc="...") {
in_port(mandatoryQueue_in, RubyRequest, mandatoryQueue, desc="...") {
if (mandatoryQueue_in.isReady()) {
peek(mandatoryQueue_in, CacheMsg) {
peek(mandatoryQueue_in, RubyRequest) {
trigger(mandatory_request_type_to_event(in_msg.Type),
in_msg.LineAddress,
getCacheEntry(in_msg.LineAddress),

11
src/mem/protocol/RubySlicc_Exports.sm
View File

@@ -213,17 +213,6 @@ enumeration(PrefetchBit, default="PrefetchBit_No", desc="...") {
L2_HW, desc="This is a L2 hardware prefetch";
}
// CacheMsg
structure(CacheMsg, desc="...", interface="Message") {
Address LineAddress, desc="Line address for this request";
Address PhysicalAddress, desc="Physical address for this request";
RubyRequestType Type, desc="Type of request (LD, ST, etc)";
Address ProgramCounter, desc="Program counter of the instruction that caused the miss";
RubyAccessMode AccessMode, desc="user/supervisor access type";
int Size, desc="size in bytes of access";
PrefetchBit Prefetch, desc="Is this a prefetch request";
}
// CacheMsg
structure(SequencerMsg, desc="...", interface="Message") {
Address LineAddress, desc="Line address for this request";

4
src/mem/protocol/RubySlicc_Profiler.sm
View File

@@ -34,10 +34,10 @@ void profileCacheCLBsize(int size, int numStaleI);
void profileMemoryCLBsize(int size, int numStaleI);
// used by 2level exclusive cache protocols
void profile_miss(CacheMsg msg);
void profile_miss(RubyRequest msg);
// used by non-fast path protocols
void profile_L1Cache_miss(CacheMsg msg, NodeID l1cacheID);
void profile_L1Cache_miss(RubyRequest msg, NodeID l1cacheID);
// used by CMP protocols
void profile_request(std::string L1CacheStateStr, std::string L2CacheStateStr,

12
src/mem/protocol/RubySlicc_Types.sm
View File

@@ -109,6 +109,16 @@ structure (Sequencer, external = "yes") {
void profileNack(Address, int, int, uint64);
}
structure(RubyRequest, desc="...", interface="Message", external="yes") {
Address LineAddress, desc="Line address for this request";
Address PhysicalAddress, desc="Physical address for this request";
RubyRequestType Type, desc="Type of request (LD, ST, etc)";
Address ProgramCounter, desc="Program counter of the instruction that caused the miss";
RubyAccessMode AccessMode, desc="user/supervisor access type";
int Size, desc="size in bytes of access";
PrefetchBit Prefetch, desc="Is this a prefetch request";
}
external_type(AbstractEntry, primitive="yes");
structure (DirectoryMemory, external = "yes") {
@@ -126,7 +136,7 @@ structure (CacheMemory, external = "yes") {
void deallocate(Address);
AbstractCacheEntry lookup(Address);
bool isTagPresent(Address);
void profileMiss(CacheMsg);
void profileMiss(RubyRequest);
void profileGenericRequest(GenericRequestType,
RubyAccessMode,