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--HG-- extra : convert_revision : 1ed206b27498641b64d7f35c74ea1f0623398d4e
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@@ -64,15 +64,9 @@
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#define IDE_COMMAND_OFFSET IDE_STATUS_OFFSET
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// PCI device specific register byte offsets
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#define PCI_IDE_TIMING 0x40
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#define PCI_SLAVE_TIMING 0x44
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#define PCI_UDMA33_CTRL 0x48
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#define PCI_UDMA33_TIMING 0x4a
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#define IDE_CTRL_CONFIG_START 0x40
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#define IDE_CTRL_CONFIG_END ((IDE_CTRL_CONFIG_START) + sizeof(pci_config_regs))
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#define IDETIM (0)
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#define SIDETIM (4)
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#define UDMACTL (5)
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#define UDMATIM (6)
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typedef enum RegType {
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COMMAND_BLOCK = 0,
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@@ -119,8 +113,30 @@ class IdeController : public PciDev
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uint8_t bmi_regs[16];
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/** Shadows of the device select bit */
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uint8_t dev[2];
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/** Registers used in PCI configuration */
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uint8_t pci_regs[8];
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/** Registers used in device specific PCI configuration */
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union {
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uint8_t data[22];
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struct {
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uint32_t idetim;
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uint8_t sidetim;
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uint8_t reserved_45;
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uint8_t reserved_46;
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uint8_t reserved_47;
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uint8_t udmactl;
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uint8_t reserved_49;
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uint16_t udmatim;
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uint8_t reserved_4c;
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uint8_t reserved_4d;
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uint8_t reserved_4e;
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uint8_t reserved_4f;
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uint8_t reserved_50;
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uint8_t reserved_51;
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uint8_t reserved_52;
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uint8_t reserved_53;
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uint16_t ideconfig;
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};
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} pci_config_regs;
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// Internal management variables
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bool io_enabled;
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