diff --git a/configs/learning_gem5/part3/msi_caches.py b/configs/learning_gem5/part3/msi_caches.py
index b719c7ab60..5aa7abed24 100644
--- a/configs/learning_gem5/part3/msi_caches.py
+++ b/configs/learning_gem5/part3/msi_caches.py
@@ -103,7 +103,7 @@ class MyCacheSystem(RubySystem):
 
         # Set up a proxy port for the system_port. Used for load binaries and
         # other functional-only things.
-        self.sys_port_proxy = RubyPortProxy()
+        self.sys_port_proxy = RubyPortProxy(ruby_system=self)
         system.system_port = self.sys_port_proxy.in_ports
 
         # Connect the cpu's cache, interrupt, and TLB ports to Ruby
diff --git a/src/mem/ruby/common/WriteMask.hh b/src/mem/ruby/common/WriteMask.hh
index e620997cd8..6b0c577454 100644
--- a/src/mem/ruby/common/WriteMask.hh
+++ b/src/mem/ruby/common/WriteMask.hh
@@ -87,6 +87,7 @@ class WriteMask
         assert(mSize == 0);
         assert(size > 0);
         mSize = size;
+        clear();
     }
 
     void
diff --git a/src/mem/ruby/protocol/chi/CHI-cache-funcs.sm b/src/mem/ruby/protocol/chi/CHI-cache-funcs.sm
index a717ede4e9..10e0f85aa3 100644
--- a/src/mem/ruby/protocol/chi/CHI-cache-funcs.sm
+++ b/src/mem/ruby/protocol/chi/CHI-cache-funcs.sm
@@ -204,6 +204,7 @@ void functionalRead(Addr addr, Packet *pkt, WriteMask &mask) {
   CacheEntry cache_entry := getCacheEntry(addr);
   DPRINTF(RubySlicc, "functionalRead %x\n", addr);
   WriteMask read_mask;
+  read_mask.setBlockSize(mask.getBlockSize());
   bool dirty := false;
   bool from_tbe := false;
 
diff --git a/src/mem/ruby/protocol/chi/CHI-mem.sm b/src/mem/ruby/protocol/chi/CHI-mem.sm
index 58f22d2007..521dd0a0d1 100644
--- a/src/mem/ruby/protocol/chi/CHI-mem.sm
+++ b/src/mem/ruby/protocol/chi/CHI-mem.sm
@@ -292,6 +292,7 @@ machine(MachineType:Memory, "Memory controller interface") :
       //TODO additional handling of partial data ??
       if (is_valid(tbe)) {
         WriteMask read_mask;
+        read_mask.setBlockSize(mask.getBlockSize());
         read_mask.setMask(addressOffset(tbe.accAddr, tbe.addr), tbe.accSize);
         read_mask.andMask(tbe.dataBlkValid);
         if (read_mask.isEmpty() == false) {
diff --git a/src/mem/ruby/system/RubySystem.cc b/src/mem/ruby/system/RubySystem.cc
index fd7b262cb1..bc2bd0cc38 100644
--- a/src/mem/ruby/system/RubySystem.cc
+++ b/src/mem/ruby/system/RubySystem.cc
@@ -660,6 +660,7 @@ RubySystem::functionalRead(PacketPtr pkt)
     // Issue functional reads to all controllers found in a stable state
     // until we get a full copy of the line
     WriteMask bytes;
+    bytes.setBlockSize(getBlockSizeBytes());
     if (ctrl_rw != nullptr) {
         ctrl_rw->functionalRead(line_address, pkt, bytes);
         // if a RW controllter has the full line that's all uptodate
diff --git a/src/mem/slicc/symbols/StateMachine.py b/src/mem/slicc/symbols/StateMachine.py
index 6202d2d239..4925765a33 100644
--- a/src/mem/slicc/symbols/StateMachine.py
+++ b/src/mem/slicc/symbols/StateMachine.py
@@ -773,10 +773,13 @@ $c_ident::init()
 
                     # For objects that require knowing the cache line size,
                     # set the value here.
-                    if vtype.c_ident in ("TBETable"):
+                    if vtype.c_ident in ("TBETable", "PerfectCacheMemory"):
                         block_size_func = "m_ruby_system->getBlockSizeBytes()"
                         code(f"(*{vid}).setBlockSize({block_size_func});")
 
+                    if vtype.c_ident in ("NetDest"):
+                        code(f"(*{vid}).setRubySystem(m_ruby_system);")
+
         for param in self.config_parameters:
             if param.type_ast.type.ident == "CacheMemory":
                 assert param.pointer
diff --git a/src/mem/slicc/symbols/Type.py b/src/mem/slicc/symbols/Type.py
index 53c8ff877e..0dc1f9bf33 100644
--- a/src/mem/slicc/symbols/Type.py
+++ b/src/mem/slicc/symbols/Type.py
@@ -274,6 +274,7 @@ $klass ${{self.c_ident}}$parent
                     code(f"\t\t, m_{dm.ident}(blockSize)")
 
             code("{")
+            code("        setRubySystem(rs);")
         elif self.isTBE:
             code("${{self.c_ident}}(int block_size)")