diff --git a/src/arch/amdgpu/gcn3/insts/op_encodings.cc b/src/arch/amdgpu/gcn3/insts/op_encodings.cc
index cbbb767382..cf20a2ea06 100644
--- a/src/arch/amdgpu/gcn3/insts/op_encodings.cc
+++ b/src/arch/amdgpu/gcn3/insts/op_encodings.cc
@@ -1277,12 +1277,12 @@ namespace Gcn3ISA
 
             reg = extData.SRSRC;
             srcOps.emplace_back(reg, getOperandSize(opNum), true,
-                                  true, false, false);
+                                  isScalarReg(reg), false, false);
             opNum++;
 
             reg = extData.SOFFSET;
             srcOps.emplace_back(reg, getOperandSize(opNum), true,
-                                  true, false, false);
+                                  isScalarReg(reg), false, false);
             opNum++;
         }
 
@@ -1368,12 +1368,12 @@ namespace Gcn3ISA
 
         reg = extData.SRSRC;
         srcOps.emplace_back(reg, getOperandSize(opNum), true,
-                              true, false, false);
+                              isScalarReg(reg), false, false);
         opNum++;
 
         reg = extData.SOFFSET;
         srcOps.emplace_back(reg, getOperandSize(opNum), true,
-                              true, false, false);
+                              isScalarReg(reg), false, false);
         opNum++;
 
         // extData.VDATA moves in the reg list depending on the instruction
@@ -1441,13 +1441,13 @@ namespace Gcn3ISA
 
         reg = extData.SRSRC;
         srcOps.emplace_back(reg, getOperandSize(opNum), true,
-                              true, false, false);
+                              isScalarReg(reg), false, false);
         opNum++;
 
         if (getNumOperands() == 4) {
             reg = extData.SSAMP;
             srcOps.emplace_back(reg, getOperandSize(opNum), true,
-                                  true, false, false);
+                                  isScalarReg(reg), false, false);
             opNum++;
         }