From 14f919a67efc49dba9d514a43fb4588975ec2591 Mon Sep 17 00:00:00 2001
From: Xuan Hu <huxuan@bosc.ac.cn>
Date: Tue, 17 Jan 2023 21:08:57 +0800
Subject: [PATCH] arch-riscv,cpu-minor: Add MinorDefaultVecFU for risc-v v-ext

Change-Id: Id5c5ae5fa1901154cadeb0a4958703f3f15d491f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67295
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
---
 src/cpu/minor/BaseMinorCPU.py | 28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/src/cpu/minor/BaseMinorCPU.py b/src/cpu/minor/BaseMinorCPU.py
index bd27b92540..c20a310447 100644
--- a/src/cpu/minor/BaseMinorCPU.py
+++ b/src/cpu/minor/BaseMinorCPU.py
@@ -250,6 +250,33 @@ class MinorDefaultMiscFU(MinorFU):
     opLat = 1
 
 
+class MinorDefaultVecFU(MinorFU):
+    opClasses = minorMakeOpClassSet(
+        [
+            "VectorUnitStrideLoad",
+            "VectorUnitStrideStore",
+            "VectorUnitStrideMaskLoad",
+            "VectorUnitStrideMaskStore",
+            "VectorStridedLoad",
+            "VectorStridedStore",
+            "VectorIndexedLoad",
+            "VectorIndexedStore",
+            "VectorUnitStrideFaultOnlyFirstLoad",
+            "VectorWholeRegisterLoad",
+            "VectorWholeRegisterStore",
+            "VectorIntegerArith",
+            "VectorFloatArith",
+            "VectorFloatConvert",
+            "VectorIntegerReduce",
+            "VectorFloatReduce",
+            "VectorMisc",
+            "VectorIntegerExtension",
+            "VectorConfig",
+        ]
+    )
+    opLat = 1
+
+
 class MinorDefaultFUPool(MinorFUPool):
     funcUnits = [
         MinorDefaultIntFU(),
@@ -260,6 +287,7 @@ class MinorDefaultFUPool(MinorFUPool):
         MinorDefaultPredFU(),
         MinorDefaultMemFU(),
         MinorDefaultMiscFU(),
+        MinorDefaultVecFU(),
     ]