Merge zizzer.eecs.umich.edu:/bk/newmem/

into  zower.eecs.umich.edu:/home/gblack/m5/newmemmemops

--HG--
extra : convert_revision : c49b760eac758dbde30867cb638fcb3b790f4721

src/python/m5/objects/BaseCPU.py

@@ -47,6 +47,7 @@ class BaseCPU(SimObject):
         "defer registration with system (for sampling)")
 
     clock = Param.Clock(Parent.clock, "clock speed")
+    phase = Param.Latency("0ns", "clock phase")
 
     _mem_ports = []