ARM: Boilerplate full-system code.

--HG--
rename : src/arch/sparc/interrupts.hh => src/arch/arm/interrupts.hh
rename : src/arch/sparc/kernel_stats.hh => src/arch/arm/kernel_stats.hh
rename : src/arch/sparc/stacktrace.cc => src/arch/arm/stacktrace.cc
rename : src/arch/sparc/system.cc => src/arch/arm/system.cc
rename : src/arch/sparc/system.hh => src/arch/arm/system.hh
rename : src/dev/sparc/T1000.py => src/dev/arm/Versatile.py
rename : src/dev/sparc/t1000.cc => src/dev/arm/versatile.cc
rename : src/dev/sparc/t1000.hh => src/dev/arm/versatile.hh

src/arch/arm/SConscript

@@ -1,6 +1,7 @@
 # -*- mode:python -*-
 
 # Copyright (c) 2007-2008 The Florida State University
+# Copyright (c) 2009 ARM Limited
 # All rights reserved.
 #
 # Redistribution and use in source and binary forms, with or without
@@ -27,6 +28,7 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #
 # Authors: Stephen Hines
+#          Ali Saidi
 
 Import('*')
 
@@ -43,6 +45,7 @@ if env['TARGET_ISA'] == 'arm':
     Source('pagetable.cc')
     Source('tlb.cc')
     Source('vtophys.cc')
+    Source('utility.cc')
 
     SimObject('ArmNativeTrace.py')
     SimObject('ArmTLB.py')
@@ -50,8 +53,12 @@ if env['TARGET_ISA'] == 'arm':
     TraceFlag('Arm')
     TraceFlag('Faults', "Trace Exceptions, interrupts, svc/swi")
     if env['FULL_SYSTEM']:
-        #Insert Full-System Files Here
-        pass
+        Source('interrupts.cc')
+        Source('stacktrace.cc')
+        Source('system.cc')
+        
+        SimObject('ArmInterrupts.py')
+        SimObject('ArmSystem.py')
     else:
         Source('process.cc')
         Source('linux/linux.cc')