arch-riscv,util: Add m5op.S for riscv to enable pseudo inst use
This change adds assembly code for riscv pseudo instructions so that they can be used with riscv benchmarks. Change-Id: Ic979fd375e7750e92f52b900bf39e351f629fe2c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38515 Reviewed-by: Jason Lowe-Power <power.jg@gmail.com> Reviewed-by: Gabe Black <gabe.black@gmail.com> Maintainer: Jason Lowe-Power <power.jg@gmail.com> Maintainer: Gabe Black <gabe.black@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Ayaz Akram
@@ -98,6 +98,7 @@ first identify what ABI(s) you're targetting.
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thumb | ARM thumb | instruction
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sparc | 64 bit SPARC | instruction
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x86 | amd64/x86_64 | instruction, address
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riscv | 64 bit RISCV | instruction
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## SCons
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@@ -166,6 +167,7 @@ scons x86.CROSS_COMPILE=x86_64-linux-gnu- build/x86/out/m5
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thumb | arm | arm-linux-gnueabihf-
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sparc | sparc64 | sparc64-linux-gnu-
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x86 | x86_64 |
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riscv | riscv64 | riscv64-linux-gnu-
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Note that the default setting for the x86 cross compiler prefix is blank,
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meaning that the native/host compiler will be used. If building on a non-x86
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@@ -254,6 +256,7 @@ varies based on the ABI.
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thumb | instruction
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sparc | instruction
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x86 | address
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riscv | instruction
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The default is usually to use a magic instruction, which for most ABIs is the
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only mechanism that's supported, and is what the m5 utility would
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32
util/m5/src/abi/riscv/SConsopts
Normal file
32
util/m5/src/abi/riscv/SConsopts
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@@ -0,0 +1,32 @@
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# Copyright 2020 Google, Inc.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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Import('*')
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env['ABI'] = 'riscv'
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get_abi_opt('CROSS_COMPILE', 'riscv64-linux-gnu-')
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get_abi_opt('QEMU_ARCH', 'riscv64')
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env['CALL_TYPE']['inst'].impl('m5op.S', 'verify_inst.cc', default=True)
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55
util/m5/src/abi/riscv/m5op.S
Normal file
55
util/m5/src/abi/riscv/m5op.S
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@@ -0,0 +1,55 @@
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/*
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* Copyright (c) 2020 The Regents of the University of California.
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* All rights reserved.
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <gem5/asm/generic/m5ops.h>
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// riscv pseudo instructions have bit 1:0 (QUADRANT) = 0x3,
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// bit 6:2 (OPCODE) = 0x1e, and bit 31:25 (M5FUNC) specifies
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// the function performed by pseudo instruction
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.macro m5op_func, name, func
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.globl \name
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\name:
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.long 0x0000007b | (\func << 25)
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ret
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.endm
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.text
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#define M5OP(name, func) m5op_func name, func;
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M5OP_FOREACH
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#undef M5OP
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47
util/m5/src/abi/riscv/verify_inst.cc
Normal file
47
util/m5/src/abi/riscv/verify_inst.cc
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@@ -0,0 +1,47 @@
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/*
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* Copyright (c) 2020 The Regents of the University of California.
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* All rights reserved.
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <gtest/gtest.h>
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#include "call_type/verify_inst.hh"
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void
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abi_verify_inst(const siginfo_t &info, int func)
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{
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EXPECT_EQ((func << 1), *(uint8_t *)((uintptr_t)info.si_addr + 3));
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}
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