config: Improve ruby simobject names
This patch attaches ruby objects to the system before the topology is created so that their simobject names read their meaningful variable names instead of their topology name.
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@@ -40,7 +40,7 @@ class Cache(RubyCache):
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def define_options(parser):
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return
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def create_system(options, phys_mem, piobus, dma_devices):
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def create_system(options, system, piobus, dma_devices):
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if buildEnv['PROTOCOL'] != 'MI_example':
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panic("This script requires the MI_example protocol to be built.")
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@@ -76,8 +76,8 @@ def create_system(options, phys_mem, piobus, dma_devices):
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cpu_seq = RubySequencer(version = i,
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icache = cache,
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dcache = cache,
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physMemPort = phys_mem.port,
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physmem = phys_mem)
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physMemPort = system.physmem.port,
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physmem = system.physmem)
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if piobus != None:
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cpu_seq.pio_port = piobus.port
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@@ -85,13 +85,16 @@ def create_system(options, phys_mem, piobus, dma_devices):
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l1_cntrl = L1Cache_Controller(version = i,
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sequencer = cpu_seq,
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cacheMemory = cache)
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exec("system.l1_cntrl%d = l1_cntrl" % i)
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#
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# Add controllers and sequencers to the appropriate lists
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#
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cpu_sequencers.append(cpu_seq)
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l1_cntrl_nodes.append(l1_cntrl)
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phys_mem_size = long(phys_mem.range.second) - long(phys_mem.range.first) + 1
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phys_mem_size = long(system.physmem.range.second) - \
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long(system.physmem.range.first) + 1
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mem_module_size = phys_mem_size / options.num_dirs
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for i in xrange(options.num_dirs):
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@@ -106,12 +109,15 @@ def create_system(options, phys_mem, piobus, dma_devices):
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dir_cntrl = Directory_Controller(version = i,
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directory = \
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RubyDirectoryMemory(version = i,
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size = dir_size,
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use_map = options.use_map,
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map_levels = options.map_levels),
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RubyDirectoryMemory( \
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version = i,
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size = dir_size,
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use_map = options.use_map,
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map_levels = \
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options.map_levels),
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memBuffer = mem_cntrl)
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exec("system.dir_cntrl%d = dir_cntrl" % i)
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dir_cntrl_nodes.append(dir_cntrl)
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for i, dma_device in enumerate(dma_devices):
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@@ -119,12 +125,13 @@ def create_system(options, phys_mem, piobus, dma_devices):
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# Create the Ruby objects associated with the dma controller
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#
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dma_seq = DMASequencer(version = i,
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physMemPort = phys_mem.port,
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physmem = phys_mem)
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physMemPort = system.physmem.port,
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physmem = system.physmem)
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dma_cntrl = DMA_Controller(version = i,
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dma_sequencer = dma_seq)
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exec("system.dma_cntrl%d = dma_cntrl" % i)
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dma_cntrl.dma_sequencer.port = dma_device.dma
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dma_cntrl_nodes.append(dma_cntrl)
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