tests: Removed m5threads tests from .testignore
This commit fixes many problems which were resulting in these tests not executing correctly. However, the m5thread tests are still failing with an `fatal:syscall set_tid_address (#166) unimplemented` error, recorded here: https://gem5.atlassian.net/browse/GEM5-747. The tests have been removed from .testignore as part of our goal of removing all tests from the .testignore file: https://gem5.atlassian.net/browse/GEM5-361 Change-Id: I287d1e126963114a791d7f3aa563a037a89b2cb7 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32916 Reviewed-by: Jason Lowe-Power <power.jg@gmail.com> Maintainer: Jason Lowe-Power <power.jg@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Bobby R. Bruce
@@ -59,17 +59,5 @@ test-insttest-rv64i-linux-TimingSimpleCPU-RISCV-aarch64-fast
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test-insttest-rv64i-linux-DerivO3CPU-RISCV-aarch64-fast
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test-insttest-linux-AtomicSimpleCPU-SPARC-aarch64-fast
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test-insttest-linux-TimingSimpleCPU-SPARC-aarch64-fast
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test-atomic-DerivO3CPU-SPARC-x86_64-opt
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test-atomic-TimingSimpleCPU-SPARC-x86_64-opt
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test-atomic-DerivO3CPU-SPARC-x86_64-debug
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test-atomic-TimingSimpleCPU-SPARC-x86_64-debug
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test-atomic-DerivO3CPU-SPARC-x86_64-fast
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test-atomic-TimingSimpleCPU-SPARC-x86_64-fast
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test-atomic-DerivO3CPU-SPARC-aarch64-opt
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test-atomic-TimingSimpleCPU-SPARC-aarch64-opt
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test-atomic-DerivO3CPU-SPARC-aarch64-debug
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test-atomic-TimingSimpleCPU-SPARC-aarch64-debug
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test-atomic-DerivO3CPU-SPARC-aarch64-fast
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test-atomic-TimingSimpleCPU-SPARC-aarch64-fast
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realview-o3-checker-ARM-x86_64-opt
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realview64-o3-checker-ARM-x86_64-opt
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@@ -26,6 +26,7 @@
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import m5
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from m5.objects import *
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from caches import *
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import sys
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import argparse
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@@ -43,6 +44,7 @@ root.system.clk_domain = SrcClockDomain()
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root.system.clk_domain.clock = '3GHz'
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root.system.clk_domain.voltage_domain = VoltageDomain()
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root.system.mem_mode = 'timing'
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root.system.mem_ranges = [AddrRange('512MB')]
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if args.cpu_type == 'DerivO3CPU':
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root.system.cpu = [DerivO3CPU(cpu_id = i)
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@@ -54,11 +56,45 @@ else:
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print("ERROR: CPU Type '" + args.cpu_type + "' not supported")
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sys.exit(1)
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root.system.membus = SystemXBar()
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root.system.membus.badaddr_responder = BadAddr()
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root.system.membus.default = root.system.membus.badaddr_responder.pio
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root.system.system_port = root.system.membus.slave
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process = Process(executable = args.cmd,
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cmd = [args.cmd, str(args.num_cores)])
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for i in range(int(args.num_cores)):
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root.system.cpu[i].workload = process
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for cpu in root.system.cpu:
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cpu.workload = process
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cpu.createThreads()
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cpu.createInterruptController()
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# Create a memory bus, a coherent crossbar, in this case
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cpu.l2bus = L2XBar()
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# Create an L1 instruction and data cache
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cpu.icache = L1ICache()
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cpu.dcache = L1DCache()
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# Connect the instruction and data caches to the CPU
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cpu.icache.connectCPU(cpu)
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cpu.dcache.connectCPU(cpu)
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# Hook the CPU ports up to the l2bus
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cpu.icache.connectBus(cpu.l2bus)
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cpu.dcache.connectBus(cpu.l2bus)
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# Create an L2 cache and connect it to the l2bus
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cpu.l2cache = L2Cache()
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cpu.l2cache.connectCPUSideBus(cpu.l2bus)
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# Connect the L2 cache to the L3 bus
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cpu.l2cache.connectMemSideBus(root.system.membus)
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root.system.mem_ctrl = DDR3_1600_8x8()
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root.system.mem_ctrl.range = root.system.mem_ranges[0]
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root.system.mem_ctrl.port = root.system.membus.master
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m5.instantiate()
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exit_event = m5.simulate()
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112
tests/gem5/m5threads_test_atomic/caches.py
Executable file
112
tests/gem5/m5threads_test_atomic/caches.py
Executable file
@@ -0,0 +1,112 @@
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# Copyright (c) 2016 Jason Lowe-Power
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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""" Caches with options for a simple gem5 configuration script
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This file contains L1 I/D and L2 caches to be used in the simple
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gem5 configuration script.
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"""
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import m5
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from m5.objects import Cache, L2XBar, StridePrefetcher, SubSystem
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from m5.params import AddrRange, AllMemory, MemorySize
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from m5.util.convert import toMemorySize
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# Some specific options for caches
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# For all options see src/mem/cache/BaseCache.py
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class L1Cache(PrefetchCache):
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"""Simple L1 Cache with default values"""
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assoc = 8
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tag_latency = 1
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data_latency = 1
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response_latency = 1
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mshrs = 16
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tgts_per_mshr = 20
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writeback_clean = True
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def __init__(self, options=None):
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super(L1Cache, self).__init__(options)
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pass
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def connectBus(self, bus):
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"""Connect this cache to a memory-side bus"""
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self.mem_side = bus.slave
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def connectCPU(self, cpu):
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"""Connect this cache's port to a CPU-side port
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This must be defined in a subclass"""
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raise NotImplementedError
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class L1ICache(L1Cache):
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"""Simple L1 instruction cache with default values"""
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# Set the size
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size = '32kB'
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def __init__(self, opts=None):
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super(L1ICache, self).__init__(opts)
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def connectCPU(self, cpu):
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"""Connect this cache's port to a CPU icache port"""
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self.cpu_side = cpu.icache_port
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class L1DCache(L1Cache):
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"""Simple L1 data cache with default values"""
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# Set the size
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size = '32kB'
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def __init__(self, opts=None):
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super(L1DCache, self).__init__(opts)
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def connectCPU(self, cpu):
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"""Connect this cache's port to a CPU dcache port"""
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self.cpu_side = cpu.dcache_port
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class L2Cache(PrefetchCache):
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"""Simple L2 Cache with default values"""
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# Default parameters
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size = '256kB'
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assoc = 16
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tag_latency = 10
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data_latency = 10
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response_latency = 1
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mshrs = 20
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tgts_per_mshr = 12
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writeback_clean = True
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def __init__(self, opts=None):
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super(L2Cache, self).__init__(opts)
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def connectCPUSideBus(self, bus):
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self.cpu_side = bus.master
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def connectMemSideBus(self, bus):
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self.mem_side = bus.slave
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7
tests/gem5/m5threads_test_atomic/ref/sparc/linux/simout → tests/gem5/m5threads_test_atomic/ref/sparc64/simout
Executable file → Normal file
7
tests/gem5/m5threads_test_atomic/ref/sparc/linux/simout → tests/gem5/m5threads_test_atomic/ref/sparc64/simout
Executable file → Normal file
@@ -1,12 +1,6 @@
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Redirecting stdout to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp/simout
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Redirecting stderr to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp/simerr
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gem5 Simulator System. http://gem5.org
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gem5 is copyrighted software; use the --copyright option for details.
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gem5 compiled Mar 29 2017 21:12:17
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gem5 started Mar 29 2017 21:12:27
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gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 42630
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command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp
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Global frequency set at 1000000000000 ticks per second
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Init done
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@@ -81,4 +75,3 @@ Iteration 9 completed
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[Iteration 10, Thread 1] Critical section done, previously next=2, now next=1
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Iteration 10 completed
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PASSED :-)
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Exiting @ tick 126524000 because exiting with last active thread context
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@@ -29,7 +29,14 @@ Test file for the m5threads atomic test
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'''
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from testlib import *
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cpu_types = ('DerivO3CPU', 'TimingSimpleCPU')
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cpu_types = (
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# We're currently ignoring these cpu_types (therefore, disabling the test)
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# due to a `fatal:syscall set_tid_address (#166)` fatal error being thrown.
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# This is documented in this gem5 Jira ticket:
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# https://gem5.atlassian.net/browse/GEM5-747
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# 'DerivO3CPU',
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# 'TimingSimpleCPU',
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)
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if config.bin_path:
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base_path = config.bin_path
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@@ -38,21 +45,23 @@ else:
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'test_atomic', 'bin')
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binary = 'test_atomic'
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url = config.resource_url + '/current/test-progs/pthread/bin/' + binary
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DownloadedProgram(url, base_path, binary)
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url = config.resource_url + '/test-progs/pthreads/sparc64/' + binary
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test_atomic = DownloadedProgram(url, base_path, binary)
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verifiers = (
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verifier.MatchStdoutNoPerf(joinpath(getcwd(), 'ref/sparc/linux/simout')),
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verifier.MatchStdoutNoPerf(joinpath(getcwd(), 'ref/sparc64/simout')),
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)
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for cpu in cpu_types:
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gem5_verify_config(
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name='test-atomic-' + cpu,
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verifiers=verifiers,
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fixtures=(test_atomic,),
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config=joinpath(getcwd(), 'atomic_system.py'),
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config_args=['--cpu-type', cpu,
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'--num-cores', '8',
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'--cmd', joinpath(base_path, binary)],
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valid_isas=('SPARC',),
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valid_hosts=constants.supported_hosts,
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length = constants.long_tag,
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)
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Block a user