From 51d492487ee6dfed9006c1c27049381b807cdb71 Mon Sep 17 00:00:00 2001 From: Harshil Patel Date: Wed, 2 Aug 2023 12:25:46 -0700 Subject: [PATCH 1/2] stdlib: stlye fix rv_type to _rvType in isa.hh and isa.cc Change-Id: I68e2b1be9150e6528693e68fb73470d158838885 --- src/arch/riscv/isa.cc | 18 +++++++++--------- src/arch/riscv/isa.hh | 8 ++++---- 2 files changed, 13 insertions(+), 13 deletions(-) diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc index 94a8239bac..266c9568b2 100644 --- a/src/arch/riscv/isa.cc +++ b/src/arch/riscv/isa.cc @@ -244,7 +244,7 @@ RegClass ccRegClass(CCRegClass, CCRegClassName, 0, debug::IntRegs); } // anonymous namespace ISA::ISA(const Params &p) : - BaseISA(p), rv_type(p.riscv_type), checkAlignment(p.check_alignment) + BaseISA(p), _rvType(p.riscv_type), checkAlignment(p.check_alignment) { _regClasses.push_back(&intRegClass); _regClasses.push_back(&floatRegClass); @@ -299,8 +299,8 @@ void ISA::clear() // mark FS is initial status.fs = INITIAL; - // rv_type dependent init. - switch (rv_type) { + // _rvType dependent init. + switch (_rvType) { case RV32: misa.rv32_mxl = 1; break; @@ -309,7 +309,7 @@ void ISA::clear() status.uxl = status.sxl = 2; break; default: - panic("%s: Unknown rv_type: %d", name(), (int)rv_type); + panic("%s: Unknown _rvType: %d", name(), (int)_rvType); } miscRegFile[MISCREG_ISA] = misa; @@ -465,7 +465,7 @@ ISA::readMiscReg(RegIndex idx) (status.xs == 3) || (status.fs == 3) || (status.vs == 3); // For RV32, the SD bit is at index 31 // For RV64, the SD bit is at index 63. - switch (rv_type) { + switch (_rvType) { case RV32: status.rv32_sd = sd_bit; break; @@ -473,7 +473,7 @@ ISA::readMiscReg(RegIndex idx) status.rv64_sd = sd_bit; break; default: - panic("%s: Unknown rv_type: %d", name(), (int)rv_type); + panic("%s: Unknown _rvType: %d", name(), (int)_rvType); } setMiscRegNoEffect(idx, status); @@ -541,7 +541,7 @@ ISA::setMiscReg(RegIndex idx, RegVal val) assert(readMiscRegNoEffect(MISCREG_PRV) == PRV_M); int regSize = 0; - switch (rv_type) { + switch (_rvType) { case RV32: regSize = 4; break; @@ -549,7 +549,7 @@ ISA::setMiscReg(RegIndex idx, RegVal val) regSize = 8; break; default: - panic("%s: Unknown rv_type: %d", name(), (int)rv_type); + panic("%s: Unknown _rvType: %d", name(), (int)_rvType); } // Specs do not seem to mention what should be @@ -643,7 +643,7 @@ ISA::setMiscReg(RegIndex idx, RegVal val) break; case MISCREG_STATUS: { - if (rv_type != RV32) { + if (_rvType != RV32) { // SXL and UXL are hard-wired to 64 bit auto cur = readMiscRegNoEffect(idx); val &= ~(STATUS_SXL_MASK | STATUS_UXL_MASK); diff --git a/src/arch/riscv/isa.hh b/src/arch/riscv/isa.hh index 31001c04b4..a2cda6b10a 100644 --- a/src/arch/riscv/isa.hh +++ b/src/arch/riscv/isa.hh @@ -70,7 +70,7 @@ enum FPUStatus class ISA : public BaseISA { protected: - RiscvType rv_type; + RiscvType _rvType; std::vector miscRegFile; bool checkAlignment; @@ -89,7 +89,7 @@ class ISA : public BaseISA PCStateBase* newPCState(Addr new_inst_addr=0) const override { - return new PCState(new_inst_addr, rv_type); + return new PCState(new_inst_addr, _rvType); } public: @@ -110,7 +110,7 @@ class ISA : public BaseISA virtual const std::unordered_map& getCSRMaskMap() const { - return CSRMasks[rv_type]; + return CSRMasks[_rvType]; } bool alignmentCheckEnabled() const { return checkAlignment; } @@ -134,7 +134,7 @@ class ISA : public BaseISA void resetThread() override; - RiscvType rvType() const { return rv_type; } + RiscvType rvType() const { return _rvType; } void clearLoadReservation(ContextID cid) From 5cfac2cc943e837a379dd36f133b2dfba4c1f4aa Mon Sep 17 00:00:00 2001 From: Harshil Patel Date: Thu, 3 Aug 2023 13:04:17 -0700 Subject: [PATCH 2/2] stdlib: Fixed stype issue pcstate.hh - Changed _rv_type to _rvType. - Changed rv_type to rvType. Change-Id: I27bdf342b038f5ebae78b104a29892684265584a --- src/arch/riscv/pcstate.hh | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/arch/riscv/pcstate.hh b/src/arch/riscv/pcstate.hh index de07145dc3..1c04cb5109 100644 --- a/src/arch/riscv/pcstate.hh +++ b/src/arch/riscv/pcstate.hh @@ -58,12 +58,12 @@ class PCState : public GenericISA::UPCState<4> { private: bool _compressed = false; - RiscvType _rv_type = RV64; + RiscvType _rvType = RV64; public: PCState() = default; PCState(const PCState &other) = default; - PCState(Addr addr, RiscvType rv_type) : UPCState(addr), _rv_type(rv_type) + PCState(Addr addr, RiscvType rvType) : UPCState(addr), _rvType(rvType) { } @@ -75,14 +75,14 @@ class PCState : public GenericISA::UPCState<4> Base::update(other); auto &pcstate = other.as(); _compressed = pcstate._compressed; - _rv_type = pcstate._rv_type; + _rvType = pcstate._rvType; } void compressed(bool c) { _compressed = c; } bool compressed() const { return _compressed; } - void rvType(RiscvType rv_type) { _rv_type = rv_type; } - RiscvType rvType() const { return _rv_type; } + void rvType(RiscvType rvType) { _rvType = rvType; } + RiscvType rvType() const { return _rvType; } bool branching() const override