diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc
index 84205eb57a..4b6f49d807 100644
--- a/src/arch/riscv/isa.cc
+++ b/src/arch/riscv/isa.cc
@@ -253,8 +253,9 @@ RegClass ccRegClass(CCRegClass, CCRegClassName, 0, debug::IntRegs);
 } // anonymous namespace
 
 ISA::ISA(const Params &p) :
-    BaseISA(p), rv_type(p.riscv_type), checkAlignment(p.check_alignment),
+    BaseISA(p), _rvType(p.riscv_type), checkAlignment(p.check_alignment),
     enableRvv(p.enable_rvv)
+
 {
     _regClasses.push_back(&intRegClass);
     _regClasses.push_back(&floatRegClass);
@@ -316,9 +317,8 @@ void ISA::clear()
     // mark FS is initial
     status.fs = INITIAL;
 
-
-    // rv_type dependent init.
-    switch (rv_type) {
+    // _rvType dependent init.
+    switch (_rvType) {
         case RV32:
           misa.rv32_mxl = 1;
           break;
@@ -331,7 +331,7 @@ void ISA::clear()
           }
           break;
         default:
-          panic("%s: Unknown rv_type: %d", name(), (int)rv_type);
+          panic("%s: Unknown _rvType: %d", name(), (int)_rvType);
     }
 
     miscRegFile[MISCREG_ISA] = misa;
@@ -487,7 +487,7 @@ ISA::readMiscReg(RegIndex idx)
                 (status.xs == 3) || (status.fs == 3) || (status.vs == 3);
             // For RV32, the SD bit is at index 31
             // For RV64, the SD bit is at index 63.
-            switch (rv_type) {
+            switch (_rvType) {
                 case RV32:
                     status.rv32_sd = sd_bit;
                     break;
@@ -495,7 +495,7 @@ ISA::readMiscReg(RegIndex idx)
                     status.rv64_sd = sd_bit;
                     break;
                 default:
-                    panic("%s: Unknown rv_type: %d", name(), (int)rv_type);
+                    panic("%s: Unknown _rvType: %d", name(), (int)_rvType);
             }
             setMiscRegNoEffect(idx, status);
 
@@ -574,7 +574,7 @@ ISA::setMiscReg(RegIndex idx, RegVal val)
                 assert(readMiscRegNoEffect(MISCREG_PRV) == PRV_M);
 
                 int regSize = 0;
-                switch (rv_type) {
+                switch (_rvType) {
                     case RV32:
                         regSize = 4;
                     break;
@@ -582,7 +582,7 @@ ISA::setMiscReg(RegIndex idx, RegVal val)
                         regSize = 8;
                     break;
                     default:
-                        panic("%s: Unknown rv_type: %d", name(), (int)rv_type);
+                        panic("%s: Unknown _rvType: %d", name(), (int)_rvType);
                 }
 
                 // Specs do not seem to mention what should be
@@ -676,7 +676,7 @@ ISA::setMiscReg(RegIndex idx, RegVal val)
             break;
           case MISCREG_STATUS:
             {
-                if (rv_type != RV32) {
+                if (_rvType != RV32) {
                     // SXL and UXL are hard-wired to 64 bit
                     auto cur = readMiscRegNoEffect(idx);
                     val &= ~(STATUS_SXL_MASK | STATUS_UXL_MASK);
diff --git a/src/arch/riscv/isa.hh b/src/arch/riscv/isa.hh
index 1be45ac7fa..f7726160c9 100644
--- a/src/arch/riscv/isa.hh
+++ b/src/arch/riscv/isa.hh
@@ -72,7 +72,7 @@ using VPUStatus = FPUStatus;
 class ISA : public BaseISA
 {
   protected:
-    RiscvType rv_type;
+    RiscvType _rvType;
     std::vector<RegVal> miscRegFile;
     bool checkAlignment;
     bool enableRvv;
@@ -92,7 +92,7 @@ class ISA : public BaseISA
     PCStateBase*
     newPCState(Addr new_inst_addr=0) const override
     {
-        return new PCState(new_inst_addr, rv_type);
+        return new PCState(new_inst_addr, _rvType);
     }
 
   public:
@@ -113,7 +113,7 @@ class ISA : public BaseISA
     virtual const std::unordered_map<int, RegVal>&
     getCSRMaskMap() const
     {
-        return CSRMasks[rv_type];
+        return CSRMasks[_rvType];
     }
 
     bool alignmentCheckEnabled() const { return checkAlignment; }
@@ -137,7 +137,7 @@ class ISA : public BaseISA
 
     void resetThread() override;
 
-    RiscvType rvType() const { return rv_type; }
+    RiscvType rvType() const { return _rvType; }
 
     bool getEnableRvv() const { return enableRvv; }
 
diff --git a/src/arch/riscv/pcstate.hh b/src/arch/riscv/pcstate.hh
index de07145dc3..1c04cb5109 100644
--- a/src/arch/riscv/pcstate.hh
+++ b/src/arch/riscv/pcstate.hh
@@ -58,12 +58,12 @@ class PCState : public GenericISA::UPCState<4>
 {
   private:
     bool _compressed = false;
-    RiscvType _rv_type = RV64;
+    RiscvType _rvType = RV64;
 
   public:
     PCState() = default;
     PCState(const PCState &other) = default;
-    PCState(Addr addr, RiscvType rv_type) : UPCState(addr), _rv_type(rv_type)
+    PCState(Addr addr, RiscvType rvType) : UPCState(addr), _rvType(rvType)
     {
     }
 
@@ -75,14 +75,14 @@ class PCState : public GenericISA::UPCState<4>
         Base::update(other);
         auto &pcstate = other.as<PCState>();
         _compressed = pcstate._compressed;
-        _rv_type = pcstate._rv_type;
+        _rvType = pcstate._rvType;
     }
 
     void compressed(bool c) { _compressed = c; }
     bool compressed() const { return _compressed; }
 
-    void rvType(RiscvType rv_type) { _rv_type = rv_type; }
-    RiscvType rvType() const { return _rv_type; }
+    void rvType(RiscvType rvType) { _rvType = rvType; }
+    RiscvType rvType() const { return _rvType; }
 
     bool
     branching() const override