From 0f54cb05936ac97d447343c58c52ac0b0b89bb39 Mon Sep 17 00:00:00 2001
From: Roger Chang <rogerycchang@google.com>
Date: Mon, 4 Sep 2023 16:13:51 +0800
Subject: [PATCH] arch-riscv: Remove check vconf done implementation

Change-Id: If633cef209390d0500c4c2c5741d56158ef26c00
---
 src/arch/riscv/decoder.cc | 31 -------------------------------
 src/arch/riscv/decoder.hh | 10 ----------
 2 files changed, 41 deletions(-)

diff --git a/src/arch/riscv/decoder.cc b/src/arch/riscv/decoder.cc
index 2070b149dd..d225871241 100644
--- a/src/arch/riscv/decoder.cc
+++ b/src/arch/riscv/decoder.cc
@@ -41,8 +41,6 @@ namespace RiscvISA
 
 Decoder::Decoder(const RiscvDecoderParams &p) : InstDecoder(p, &machInst)
 {
-    ISA *isa = dynamic_cast<ISA*>(p.isa);
-    enableRvv = isa->getEnableRvv();
     reset();
 }
 
@@ -50,7 +48,6 @@ void Decoder::reset()
 {
     aligned = true;
     mid = false;
-    vConfigDone = true;
     machInst = 0;
     emi = 0;
 }
@@ -58,19 +55,6 @@ void Decoder::reset()
 void
 Decoder::moreBytes(const PCStateBase &pc, Addr fetchPC)
 {
-    // TODO: Current vsetvl instructions stall decode. Future fixes should
-    // enable speculation, and this code will be removed.
-    if (GEM5_UNLIKELY(!this->vConfigDone)) {
-        fatal_if(!enableRvv,
-            "Vector extension is not enabled for this CPU type\n"
-            "You can manually enable vector extensions by setting rvv_enabled "
-            "to true for each ISA object after `createThreads()`\n");
-        DPRINTF(Decode, "Waiting for vset*vl* to be executed\n");
-        instDone = false;
-        outOfBytes = false;
-        return;
-    }
-
     // The MSB of the upper and lower halves of a machine instruction.
     constexpr size_t max_bit = sizeof(machInst) * 8 - 1;
     constexpr size_t mid_bit = sizeof(machInst) * 4 - 1;
@@ -100,12 +84,6 @@ Decoder::moreBytes(const PCStateBase &pc, Addr fetchPC)
             instDone = compressed(emi);
         }
     }
-    if (instDone) {
-
-        if (vconf(emi)) {
-            this->vConfigDone = false; // set true when vconfig inst execute
-        }
-    }
 }
 
 StaticInstPtr
@@ -147,14 +125,5 @@ Decoder::decode(PCStateBase &_next_pc)
     return decode(emi, next_pc.instAddr());
 }
 
-void
-Decoder::setVlAndVtype(uint32_t vl, VTYPE vtype)
-{
-    this->machVtype = vtype;
-    this->machVl = vl;
-
-    this->vConfigDone = true;
-}
-
 } // namespace RiscvISA
 } // namespace gem5
diff --git a/src/arch/riscv/decoder.hh b/src/arch/riscv/decoder.hh
index 1f510e8280..6ce72ee35a 100644
--- a/src/arch/riscv/decoder.hh
+++ b/src/arch/riscv/decoder.hh
@@ -54,17 +54,12 @@ class Decoder : public InstDecoder
     decode_cache::InstMap<ExtMachInst> instMap;
     bool aligned;
     bool mid;
-    bool vConfigDone;
 
   protected:
     //The extended machine instruction being generated
     ExtMachInst emi;
     uint32_t machInst;
 
-    bool enableRvv = false;
-    VTYPE machVtype;
-    uint32_t machVl;
-
     StaticInstPtr decodeInst(ExtMachInst mach_inst);
 
     /// Decode a machine instruction.
@@ -78,17 +73,12 @@ class Decoder : public InstDecoder
     void reset() override;
 
     inline bool compressed(ExtMachInst inst) { return inst.quadRant < 0x3; }
-    inline bool vconf(ExtMachInst inst) {
-      return inst.opcode == 0b1010111u && inst.funct3 == 0b111u;
-    }
 
     //Use this to give data to the decoder. This should be used
     //when there is control flow.
     void moreBytes(const PCStateBase &pc, Addr fetchPC) override;
 
     StaticInstPtr decode(PCStateBase &nextPC) override;
-
-    void setVlAndVtype(uint32_t vl, VTYPE vtype);
 };
 
 } // namespace RiscvISA