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arch-arm: DomainType is not specific to the TlbEntry

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Change-Id: I626c79973fcd60b1be36a965923999a1c9a9bc54
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
This commit is contained in:
Giacomo Travaglini
2024-10-18 13:44:03 +01:00
parent d3cdd2dc17
commit 0f1436ba5f
10 changed files with 44 additions and 44 deletions
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10
src/arch/arm/faults.hh
View File

@@ -473,7 +473,7 @@ class AbortFault : public ArmFaultVals<T>
*/
Addr OVAddr;
bool write;
TlbEntry::DomainType domain;
DomainType domain;
uint8_t source;
uint8_t srcEncoded;
bool stage2;
@@ -482,7 +482,7 @@ class AbortFault : public ArmFaultVals<T>
ArmFault::DebugType debugType;
public:
AbortFault(Addr _faultAddr, bool _write, TlbEntry::DomainType _domain,
AbortFault(Addr _faultAddr, bool _write, DomainType _domain,
uint8_t _source, bool _stage2,
TranMethod _tranMethod = TranMethod::UnknownTran,
ArmFault::DebugType _debug = ArmFault::NODEBUG) :
@@ -518,7 +518,7 @@ class PrefetchAbort : public AbortFault<PrefetchAbort>
PrefetchAbort(Addr _addr, uint8_t _source, bool _stage2 = false,
TranMethod _tran_method = TranMethod::UnknownTran,
ArmFault::DebugType _debug = ArmFault::NODEBUG) :
AbortFault<PrefetchAbort>(_addr, false, TlbEntry::DomainType::NoAccess,
AbortFault<PrefetchAbort>(_addr, false, DomainType::NoAccess,
_source, _stage2, _tran_method, _debug)
{}
@@ -549,7 +549,7 @@ class DataAbort : public AbortFault<DataAbort>
bool sf;
bool ar;
DataAbort(Addr _addr, TlbEntry::DomainType _domain, bool _write, uint8_t _source,
DataAbort(Addr _addr, DomainType _domain, bool _write, uint8_t _source,
bool _stage2=false,
TranMethod _tran_method=TranMethod::UnknownTran,
ArmFault::DebugType _debug_type=ArmFault::NODEBUG) :
@@ -577,7 +577,7 @@ class VirtualDataAbort : public AbortFault<VirtualDataAbort>
static const MiscRegIndex FarIndex = MISCREG_DFAR;
static const MiscRegIndex HFarIndex = MISCREG_HDFAR;
VirtualDataAbort(Addr _addr, TlbEntry::DomainType _domain, bool _write,
VirtualDataAbort(Addr _addr, DomainType _domain, bool _write,
uint8_t _source) :
AbortFault<VirtualDataAbort>(_addr, _write, _domain, _source, false)
{}

2
src/arch/arm/interrupts.hh
View File

@@ -235,7 +235,7 @@ class Interrupts : public BaseInterrupts
return std::make_shared<SystemError>();
if (hcr.va && takeVirtualInt(INT_VIRT_ABT))
return std::make_shared<VirtualDataAbort>(
0, TlbEntry::DomainType::NoAccess, false,
0, DomainType::NoAccess, false,
ArmFault::AsynchronousExternalAbort);
if (interrupts[INT_RST])
return std::make_shared<Reset>();

16
src/arch/arm/mmu.cc
View File

@@ -207,7 +207,7 @@ MMU::testAndFinalize(const RequestPtr &req,
{
// If we don't have a valid tlb entry it means virtual memory
// is not enabled
auto domain = te ? te-> domain : TlbEntry::DomainType::NoAccess;
auto domain = te ? te-> domain : DomainType::NoAccess;
mpam::tagRequest(tc, req, mode == Execute);
@@ -277,7 +277,7 @@ MMU::translateSe(const RequestPtr &req, ThreadContext *tc, Mode mode,
// LPAE is always disabled in SE mode
return std::make_shared<DataAbort>(
vaddr_tainted,
TlbEntry::DomainType::NoAccess, is_write,
DomainType::NoAccess, is_write,
ArmFault::AlignmentFault, state.isStage2,
TranMethod::VmsaTran);
}
@@ -343,7 +343,7 @@ MMU::checkPermissions(TlbEntry *te, const RequestPtr &req, Mode mode,
if (vaddr & mask(flags & AlignmentMask)) {
stats.alignFaults++;
return std::make_shared<DataAbort>(
vaddr, TlbEntry::DomainType::NoAccess, is_write,
vaddr, DomainType::NoAccess, is_write,
ArmFault::AlignmentFault, state.isStage2,
tran_method);
}
@@ -538,7 +538,7 @@ MMU::checkPermissions64(TlbEntry *te, const RequestPtr &req, Mode mode,
stats.alignFaults++;
return std::make_shared<DataAbort>(
vaddr_tainted,
TlbEntry::DomainType::NoAccess,
DomainType::NoAccess,
is_atomic ? false : is_write,
ArmFault::AlignmentFault, state.isStage2,
TranMethod::LpaeTran);
@@ -831,7 +831,7 @@ MMU::translateMmuOff(ThreadContext *tc, const RequestPtr &req, Mode mode,
TranMethod::LpaeTran);
else
f = std::make_shared<DataAbort>( vaddr,
TlbEntry::DomainType::NoAccess,
DomainType::NoAccess,
is_atomic ? false : mode==Write,
ArmFault::AddressSizeLL, state.isStage2,
TranMethod::LpaeTran);
@@ -934,7 +934,7 @@ MMU::translateMmuOn(ThreadContext* tc, const RequestPtr &req, Mode mode,
bool is_write = (mode == Write);
return std::make_shared<DataAbort>(
vaddr_tainted,
TlbEntry::DomainType::NoAccess, is_write,
DomainType::NoAccess, is_write,
ArmFault::AlignmentFault, state.isStage2,
tran_method);
}
@@ -996,7 +996,7 @@ MMU::translateFs(const RequestPtr &req, ThreadContext *tc, Mode mode,
stats.alignFaults++;
return std::make_shared<DataAbort>(
vaddr_tainted,
TlbEntry::DomainType::NoAccess, is_write,
DomainType::NoAccess, is_write,
ArmFault::AlignmentFault, state.isStage2,
tran_method);
}
@@ -1590,7 +1590,7 @@ MMU::setTestInterface(SimObject *_ti)
Fault
MMU::testTranslation(const RequestPtr &req, Mode mode,
TlbEntry::DomainType domain, CachedState &state) const
DomainType domain, CachedState &state) const
{
if (!test || !req->hasSize() || req->getSize() == 0 ||
req->isCacheMaintenance()) {

2
src/arch/arm/mmu.hh
View File

@@ -463,7 +463,7 @@ class MMU : public BaseMMU
void setTestInterface(SimObject *ti);
Fault testTranslation(const RequestPtr &req, Mode mode,
TlbEntry::DomainType domain, CachedState &state) const;
DomainType domain, CachedState &state) const;
protected:
bool checkWalkCache() const;

8
src/arch/arm/pagetable.hh
View File

@@ -174,14 +174,6 @@ struct TlbEntry : public Serializable
Normal
};
enum class DomainType : std::uint8_t
{
NoAccess = 0,
Client,
Reserved,
Manager
};
struct Lookup
{
// virtual address

2
src/arch/arm/self_debug.cc
View File

@@ -145,7 +145,7 @@ SelfDebug::triggerWatchpointException(ThreadContext *tc, Addr vaddr,
ArmFault::DebugType d = cm? ArmFault::WPOINT_CM:
ArmFault::WPOINT_NOCM;
return std::make_shared<DataAbort>(vaddr,
TlbEntry::DomainType::NoAccess,
DomainType::NoAccess,
write, ArmFault::DebugEvent, cm,
TranMethod::UnknownTran, d);
} else {

22
src/arch/arm/table_walker.cc
View File

@@ -644,7 +644,7 @@ TableWalker::processWalk()
else
return std::make_shared<DataAbort>(
currState->vaddr_tainted,
TlbEntry::DomainType::NoAccess,
DomainType::NoAccess,
is_atomic ? false : currState->isWrite,
ArmFault::TranslationLL + LookupLevel::L1, isStage2,
TranMethod::VmsaTran);
@@ -665,7 +665,7 @@ TableWalker::processWalk()
else
return std::make_shared<DataAbort>(
currState->vaddr_tainted,
TlbEntry::DomainType::NoAccess,
DomainType::NoAccess,
is_atomic ? false : currState->isWrite,
ArmFault::TranslationLL + LookupLevel::L1, isStage2,
TranMethod::VmsaTran);
@@ -762,7 +762,7 @@ TableWalker::processWalkLPAE()
else
return std::make_shared<DataAbort>(
currState->vaddr_tainted,
TlbEntry::DomainType::NoAccess,
DomainType::NoAccess,
is_atomic ? false : currState->isWrite,
ArmFault::TranslationLL + LookupLevel::L1,
isStage2,
@@ -788,7 +788,7 @@ TableWalker::processWalkLPAE()
else
return std::make_shared<DataAbort>(
currState->vaddr_tainted,
TlbEntry::DomainType::NoAccess,
DomainType::NoAccess,
is_atomic ? false : currState->isWrite,
ArmFault::TranslationLL + LookupLevel::L1,
isStage2,
@@ -813,7 +813,7 @@ TableWalker::processWalkLPAE()
else
return std::make_shared<DataAbort>(
currState->vaddr_tainted,
TlbEntry::DomainType::NoAccess,
DomainType::NoAccess,
is_atomic ? false : currState->isWrite,
ArmFault::TranslationLL + LookupLevel::L1,
isStage2, TranMethod::LpaeTran);
@@ -1078,7 +1078,7 @@ TableWalker::processWalkAArch64()
} else {
return std::make_shared<DataAbort>(
currState->vaddr_tainted,
TlbEntry::DomainType::NoAccess,
DomainType::NoAccess,
is_atomic ? false : currState->isWrite,
ArmFault::TranslationLL + LookupLevel::L0,
isStage2, TranMethod::LpaeTran);
@@ -1115,7 +1115,7 @@ TableWalker::processWalkAArch64()
else
return std::make_shared<DataAbort>(
currState->vaddr_tainted,
TlbEntry::DomainType::NoAccess,
DomainType::NoAccess,
is_atomic ? false : currState->isWrite,
ArmFault::AddressSizeLL + start_lookup_level,
isStage2,
@@ -1692,7 +1692,7 @@ TableWalker::doL1Descriptor()
currState->fault =
std::make_shared<DataAbort>(
currState->vaddr_tainted,
TlbEntry::DomainType::NoAccess,
DomainType::NoAccess,
is_atomic ? false : currState->isWrite,
ArmFault::TranslationLL + LookupLevel::L1, isStage2,
TranMethod::VmsaTran);
@@ -1762,7 +1762,7 @@ TableWalker::generateLongDescFault(ArmFault::FaultSource src)
} else {
return std::make_shared<DataAbort>(
currState->vaddr_tainted,
TlbEntry::DomainType::NoAccess,
DomainType::NoAccess,
currState->req->isAtomic() ? false : currState->isWrite,
src + currState->longDesc.lookupLevel,
isStage2,
@@ -1973,7 +1973,7 @@ TableWalker::doL2Descriptor()
currState->fault = std::make_shared<DataAbort>(
currState->vaddr_tainted,
TlbEntry::DomainType::NoAccess,
DomainType::NoAccess,
is_atomic ? false : currState->isWrite,
ArmFault::AccessFlagLL + LookupLevel::L2, isStage2,
TranMethod::VmsaTran);
@@ -2427,7 +2427,7 @@ TableWalker::pendingChange()
}
Fault
TableWalker::testWalk(const RequestPtr &walk_req, TlbEntry::DomainType domain,
TableWalker::testWalk(const RequestPtr &walk_req, DomainType domain,
LookupLevel lookup_level)
{
if (!test) {

14
src/arch/arm/table_walker.hh
View File

@@ -79,7 +79,7 @@ class TableWalker : public ClockedObject
LookupLevel lookupLevel;
virtual Addr pfn() const = 0;
virtual TlbEntry::DomainType domain() const = 0;
virtual DomainType domain() const = 0;
virtual bool xn() const = 0;
virtual uint8_t ap() const = 0;
virtual bool global(WalkerState *currState) const = 0;
@@ -209,10 +209,10 @@ class TableWalker : public ClockedObject
}
/** Domain Client/Manager: ARM DDI 0406B: B3-31 */
TlbEntry::DomainType
DomainType
domain() const override
{
return static_cast<TlbEntry::DomainType>(bits(data, 8, 5));
return static_cast<DomainType>(bits(data, 8, 5));
}
/** Address of L2 descriptor if it exists */
@@ -316,7 +316,7 @@ class TableWalker : public ClockedObject
return "Inserting L2 Descriptor into TLB\n";
}
TlbEntry::DomainType
DomainType
domain() const override
{
return l1Parent->domain();
@@ -744,11 +744,11 @@ class TableWalker : public ClockedObject
return ((!rw) << 2) | (user << 1);
}
TlbEntry::DomainType
DomainType
domain() const override
{
// Long-desc. format only supports Client domain
return TlbEntry::DomainType::Client;
return DomainType::Client;
}
/** Attribute index */
@@ -1249,7 +1249,7 @@ class TableWalker : public ClockedObject
void setTestInterface(TlbTestInterface *ti);
Fault testWalk(const RequestPtr &walk_req, TlbEntry::DomainType domain,
Fault testWalk(const RequestPtr &walk_req, DomainType domain,
LookupLevel lookup_level);
};

4
src/arch/arm/tlb.hh
View File

@@ -79,7 +79,7 @@ class TlbTestInterface
*/
virtual Fault translationCheck(const RequestPtr &req, bool is_priv,
BaseMMU::Mode mode,
TlbEntry::DomainType domain) = 0;
DomainType domain) = 0;
/**
* Check if a page table walker access should be forced to fail.
@@ -95,7 +95,7 @@ class TlbTestInterface
virtual Fault walkCheck(const RequestPtr &walk_req,
Addr va, bool is_secure,
Addr is_priv, BaseMMU::Mode mode,
TlbEntry::DomainType domain,
DomainType domain,
enums::ArmLookupLevel lookup_level) = 0;
};

8
src/arch/arm/types.hh
View File

@@ -289,6 +289,14 @@ namespace ArmISA
UnknownTran
};
enum class DomainType : std::uint8_t
{
NoAccess = 0,
Client,
Reserved,
Manager
};
enum ExceptionLevel
{
EL0 = 0,