From 0f0317ad16ba810f99cd8a7cdae4a9f847481ff0 Mon Sep 17 00:00:00 2001 From: Harshil Patel Date: Wed, 6 Dec 2023 20:10:56 -0800 Subject: [PATCH] Arch-riscv: Add chosen node Change-Id: I458665caec08856cd8e61d2cd7a5b0dc5c35d469 --- .../gem5/prebuilt/riscvmatched/riscvmatched_board.py | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/src/python/gem5/prebuilt/riscvmatched/riscvmatched_board.py b/src/python/gem5/prebuilt/riscvmatched/riscvmatched_board.py index f827ec7bff..f4e4b381a1 100644 --- a/src/python/gem5/prebuilt/riscvmatched/riscvmatched_board.py +++ b/src/python/gem5/prebuilt/riscvmatched/riscvmatched_board.py @@ -348,6 +348,12 @@ class RISCVMatchedBoard( ) root.append(node) + node = FdtNode(f"chosen") + bootargs = self.workload.command_line + node.append(FdtPropertyStrings("bootargs", [bootargs])) + node.append(FdtPropertyStrings("stdout-path", ["/uart@10000000"])) + root.append(node) + # See Documentation/devicetree/bindings/riscv/cpus.txt for details. cpus_node = FdtNode("cpus") cpus_state = FdtState(addr_cells=1, size_cells=0) @@ -520,7 +526,7 @@ class RISCVMatchedBoard( uart_node.append( FdtPropertyWords("interrupt-parent", soc_state.phandle(plic)) ) - uart_node.appendCompatible(["ns8250"]) + uart_node.appendCompatible(["ns8250", "ns16550a"]) soc_node.append(uart_node) # VirtIO MMIO disk node