diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc
index b716ba93fb..c4331a46f5 100644
--- a/src/arch/arm/utility.cc
+++ b/src/arch/arm/utility.cc
@@ -45,6 +45,7 @@
 #include "arch/arm/page_size.hh"
 #include "arch/arm/regs/cc.hh"
 #include "arch/arm/regs/int.hh"
+#include "arch/arm/regs/vec.hh"
 #include "arch/arm/system.hh"
 #include "base/compiler.hh"
 #include "cpu/base.hh"
@@ -1327,5 +1328,32 @@ encodePhysAddrRange64(int pa_size)
     }
 }
 
+void
+syncVecRegsToElems(ThreadContext *tc)
+{
+    for (int ri = 0; ri < NumVecRegs; ri++) {
+        RegId reg_id(VecRegClass, ri);
+        const VecRegContainer &reg = tc->readVecReg(reg_id);
+        for (int ei = 0; ei < NumVecElemPerVecReg; ei++) {
+            RegId elem_id(VecElemClass, ri, ei);
+            tc->setVecElem(elem_id, reg.as<VecElem>()[ei]);
+        }
+    }
+}
+
+void
+syncVecElemsToRegs(ThreadContext *tc)
+{
+    for (int ri = 0; ri < NumVecRegs; ri++) {
+        VecRegContainer reg;
+        for (int ei = 0; ei < NumVecElemPerVecReg; ei++) {
+            RegId elem_id(VecElemClass, ri, ei);
+            reg.as<VecElem>()[ei] = tc->readVecElem(elem_id);
+        }
+        RegId reg_id(VecRegClass, ri);
+        tc->setVecReg(reg_id, reg);
+    }
+}
+
 } // namespace ArmISA
 } // namespace gem5
diff --git a/src/arch/arm/utility.hh b/src/arch/arm/utility.hh
index 9667d479b0..7d9affa8dd 100644
--- a/src/arch/arm/utility.hh
+++ b/src/arch/arm/utility.hh
@@ -393,6 +393,9 @@ byteOrder(const ThreadContext *tc)
 
 bool isUnpriviledgeAccess(ThreadContext *tc);
 
+void syncVecRegsToElems(ThreadContext *tc);
+void syncVecElemsToRegs(ThreadContext *tc);
+
 } // namespace ArmISA
 } // namespace gem5