diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index a530001ae3..6817db41ef 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -701,8 +701,10 @@ Cache::recvTimingReq(PacketPtr pkt)
             }
         } else {
             // no MSHR
-            if (!pkt->req->isUncacheable()) {
-                assert(pkt->req->masterId() < system->maxMasters());
+            assert(pkt->req->masterId() < system->maxMasters());
+            if (pkt->req->isUncacheable()) {
+                mshr_uncacheable[pkt->cmdToIndex()][pkt->req->masterId()]++;
+            } else {
                 mshr_misses[pkt->cmdToIndex()][pkt->req->masterId()]++;
             }