diff --git a/src/arch/arm/kvm/gic.cc b/src/arch/arm/kvm/gic.cc
index b0c3d966c4..5ce148e93d 100644
--- a/src/arch/arm/kvm/gic.cc
+++ b/src/arch/arm/kvm/gic.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2017 ARM Limited
+ * Copyright (c) 2015-2017, 2021 Arm Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -273,18 +273,16 @@ MuxingKvmGic::clearPPInt(uint32_t num, uint32_t cpu)
     kernelGic->clearPPI(cpu, num);
 }
 
-void
-MuxingKvmGic::updateIntState(int hint)
+bool
+MuxingKvmGic::blockIntUpdate() const
 {
-    // During Kvm->GicV2 state transfer, writes to the GicV2 will call
+    // During Kvm->Gic state transfer, writes to the Gic will call
     // updateIntState() which can post an interrupt.  Since we're only
-    // using the GicV2 model for holding state in this circumstance, we
+    // using the Gic model for holding state in this circumstance, we
     // short-circuit this behavior, as the GicV2 is not actually active.
-    if (!usingKvm)
-        return GicV2::updateIntState(hint);
+    return usingKvm;
 }
 
-
 void
 MuxingKvmGic::fromGicV2ToKvm()
 {
diff --git a/src/arch/arm/kvm/gic.hh b/src/arch/arm/kvm/gic.hh
index 71ec3bc898..a8352086a8 100644
--- a/src/arch/arm/kvm/gic.hh
+++ b/src/arch/arm/kvm/gic.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2017 ARM Limited
+ * Copyright (c) 2015-2017, 2021 Arm Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -189,8 +189,8 @@ class MuxingKvmGic : public GicV2
     void sendPPInt(uint32_t num, uint32_t cpu) override;
     void clearPPInt(uint32_t num, uint32_t cpu) override;
 
-  protected: // GicV2
-    void updateIntState(int hint) override;
+  protected: // BaseGic
+    bool blockIntUpdate() const override;
 
   protected:
     /** System this interrupt controller belongs to */
diff --git a/src/dev/arm/gic_v2.hh b/src/dev/arm/gic_v2.hh
index 577f78ecd3..5562419194 100644
--- a/src/dev/arm/gic_v2.hh
+++ b/src/dev/arm/gic_v2.hh
@@ -448,7 +448,7 @@ class GicV2 : public BaseGic, public BaseGicRegisters
     /** See if some processor interrupt flags need to be enabled/disabled
      * @param hint which set of interrupts needs to be checked
      */
-    virtual void updateIntState(int hint);
+    void updateIntState(int hint);
 
     /** Update the register that records priority of the highest priority
      *  active interrupt*/