configs/inorder: add options for switch-on-miss to inorder cpu

This commit is contained in:
Korey Sewell
2010-01-31 18:25:13 -05:00
parent 7b3b362ba5
commit 0e96798fe0
3 changed files with 24 additions and 2 deletions

View File

@@ -30,10 +30,15 @@ from m5.params import *
from m5.proxy import *
from BaseCPU import BaseCPU
class ThreadModel(Enum):
vals = ['Single', 'SMT', 'SwitchOnCacheMiss']
class InOrderCPU(BaseCPU):
type = 'InOrderCPU'
activity = Param.Unsigned(0, "Initial count")
threadModel = Param.ThreadModel('SMT', "Multithreading model (SE-MODE only)")
cachePorts = Param.Unsigned(2, "Cache Ports")
stageWidth = Param.Unsigned(1, "Stage width")