From 0e4f82a1194a926498b791bc9dd55686dbad5bab Mon Sep 17 00:00:00 2001 From: Roger Chang Date: Mon, 30 Oct 2023 15:59:32 +0800 Subject: [PATCH] arch-riscv: define the CSR masks for each privilege modes Change-Id: I9936d9bc816921a827b94550847d4898b3aa3292 --- src/arch/riscv/isa.hh | 2 +- src/arch/riscv/regs/misc.hh | 383 +++++++++++++++++++++++++++++------ src/arch/riscv/remote_gdb.cc | 81 +++++--- 3 files changed, 366 insertions(+), 100 deletions(-) diff --git a/src/arch/riscv/isa.hh b/src/arch/riscv/isa.hh index 6a3547ab2c..9a24a76745 100644 --- a/src/arch/riscv/isa.hh +++ b/src/arch/riscv/isa.hh @@ -129,7 +129,7 @@ class ISA : public BaseISA virtual const std::unordered_map& getCSRMaskMap() const { - return CSRMasks[_rvType]; + return CSRMasks[_rvType][_privilegeModeSet]; } bool alignmentCheckEnabled() const { return checkAlignment; } diff --git a/src/arch/riscv/regs/misc.hh b/src/arch/riscv/regs/misc.hh index d36776d7ef..7f7621f8ea 100644 --- a/src/arch/riscv/regs/misc.hh +++ b/src/arch/riscv/regs/misc.hh @@ -1118,41 +1118,137 @@ const RegVal STATUS_UPIE_MASK = 1ULL << 4; const RegVal STATUS_MIE_MASK = 1ULL << 3; const RegVal STATUS_SIE_MASK = 1ULL << 1; const RegVal STATUS_UIE_MASK = 1ULL << 0; -const RegVal MSTATUS_MASKS[enums::Num_RiscvType] = { - [RV32] = STATUS_SD_MASKS[RV32] | STATUS_TSR_MASK | STATUS_TW_MASK | - STATUS_TVM_MASK | STATUS_MXR_MASK | STATUS_SUM_MASK | - STATUS_MPRV_MASK | STATUS_XS_MASK | STATUS_FS_MASK | - STATUS_VS_MASK | STATUS_MPP_MASK | STATUS_SPP_MASK | - STATUS_MPIE_MASK | STATUS_SPIE_MASK | STATUS_UPIE_MASK | - STATUS_MIE_MASK | STATUS_SIE_MASK | STATUS_UIE_MASK, - [RV64] = STATUS_SD_MASKS[RV64] | STATUS_MBE_MASK[RV64] | - STATUS_SBE_MASK[RV64] | STATUS_SXL_MASK | STATUS_UXL_MASK | - STATUS_TSR_MASK | STATUS_TW_MASK | STATUS_TVM_MASK | - STATUS_MXR_MASK | STATUS_SUM_MASK | STATUS_MPRV_MASK | - STATUS_XS_MASK | STATUS_FS_MASK | STATUS_VS_MASK| - STATUS_MPP_MASK | STATUS_SPP_MASK | STATUS_MPIE_MASK | - STATUS_SPIE_MASK | STATUS_UPIE_MASK | STATUS_MIE_MASK | - STATUS_SIE_MASK | STATUS_UIE_MASK, +const RegVal +MSTATUS_MASKS[enums::Num_RiscvType][enums::Num_PrivilegeModeSet] = { + [RV32] = { + [enums::M] = STATUS_SD_MASKS[RV32] | + STATUS_XS_MASK | STATUS_FS_MASK | STATUS_VS_MASK | + STATUS_MPIE_MASK | STATUS_MIE_MASK, + [enums::MU] = STATUS_SD_MASKS[RV32] | STATUS_TW_MASK | + STATUS_MPRV_MASK | + STATUS_XS_MASK | STATUS_FS_MASK | STATUS_VS_MASK | + STATUS_MPP_MASK | STATUS_MPIE_MASK | STATUS_MIE_MASK, + [enums::MNU] = STATUS_SD_MASKS[RV32] | STATUS_TW_MASK | + STATUS_MPRV_MASK | + STATUS_XS_MASK | STATUS_FS_MASK | STATUS_VS_MASK | + STATUS_MPP_MASK | + STATUS_MPIE_MASK | STATUS_UPIE_MASK | + STATUS_MIE_MASK | STATUS_UIE_MASK, + [enums::MSU] = STATUS_SD_MASKS[RV32] | STATUS_TSR_MASK | + STATUS_TW_MASK | STATUS_TVM_MASK | STATUS_MXR_MASK | + STATUS_SUM_MASK | STATUS_MPRV_MASK | + STATUS_XS_MASK | STATUS_FS_MASK | STATUS_VS_MASK | + STATUS_MPP_MASK | STATUS_SPP_MASK | + STATUS_MPIE_MASK | STATUS_SPIE_MASK | + STATUS_MIE_MASK | STATUS_SIE_MASK, + [enums::MNSU] = STATUS_SD_MASKS[RV32] | STATUS_TSR_MASK | + STATUS_TW_MASK | STATUS_TVM_MASK | STATUS_MXR_MASK | + STATUS_SUM_MASK | STATUS_MPRV_MASK | + STATUS_XS_MASK | STATUS_FS_MASK | STATUS_VS_MASK | + STATUS_MPP_MASK | STATUS_SPP_MASK | + STATUS_MPIE_MASK | STATUS_SPIE_MASK | + STATUS_UPIE_MASK | STATUS_MIE_MASK | STATUS_SIE_MASK | + STATUS_UIE_MASK, + }, + [RV64] = { + [enums::M] = STATUS_SD_MASKS[RV64] | STATUS_MBE_MASK[RV64] | + STATUS_XS_MASK | STATUS_FS_MASK | STATUS_VS_MASK | + STATUS_MPIE_MASK | STATUS_MIE_MASK, + [enums::MU] = STATUS_SD_MASKS[RV64] | STATUS_MBE_MASK[RV64] | + STATUS_UXL_MASK | STATUS_TW_MASK | STATUS_MPRV_MASK | + STATUS_XS_MASK | STATUS_FS_MASK | STATUS_VS_MASK | + STATUS_MPP_MASK | STATUS_MPIE_MASK | STATUS_MIE_MASK, + [enums::MNU] = STATUS_SD_MASKS[RV64] | STATUS_MBE_MASK[RV64] | + STATUS_UXL_MASK | STATUS_TW_MASK | STATUS_MPRV_MASK | + STATUS_XS_MASK | STATUS_FS_MASK | STATUS_VS_MASK | + STATUS_MPP_MASK | + STATUS_MPIE_MASK | STATUS_UPIE_MASK | + STATUS_MIE_MASK | STATUS_UIE_MASK, + [enums::MSU] = STATUS_SD_MASKS[RV64] | + STATUS_MBE_MASK[RV64] | STATUS_SBE_MASK[RV64] | + STATUS_SXL_MASK | STATUS_UXL_MASK | + STATUS_TSR_MASK | STATUS_TW_MASK | STATUS_TVM_MASK | + STATUS_MXR_MASK | STATUS_SUM_MASK | STATUS_MPRV_MASK | + STATUS_XS_MASK | STATUS_FS_MASK | STATUS_VS_MASK | + STATUS_MPP_MASK | STATUS_SPP_MASK | + STATUS_MPIE_MASK | STATUS_SPIE_MASK | + STATUS_MIE_MASK | STATUS_SIE_MASK, + [enums::MNSU] = STATUS_SD_MASKS[RV64] | + STATUS_MBE_MASK[RV64] | STATUS_SBE_MASK[RV64] | + STATUS_SXL_MASK | STATUS_UXL_MASK | + STATUS_TSR_MASK | STATUS_TW_MASK | STATUS_TVM_MASK | + STATUS_MXR_MASK | STATUS_SUM_MASK | STATUS_MPRV_MASK | + STATUS_XS_MASK | STATUS_FS_MASK | STATUS_VS_MASK | + STATUS_MPP_MASK | STATUS_SPP_MASK | + STATUS_MPIE_MASK | STATUS_SPIE_MASK | STATUS_UPIE_MASK | + STATUS_MIE_MASK | STATUS_SIE_MASK | STATUS_UIE_MASK, + }, }; // rv32 only -const RegVal MSTATUSH_MASKS = STATUS_MBE_MASK[RV32] | STATUS_SBE_MASK[RV32]; -const RegVal SSTATUS_MASKS[enums::Num_RiscvType] = { - [RV32] = STATUS_SD_MASKS[RV32] | STATUS_MXR_MASK | STATUS_SUM_MASK | - STATUS_XS_MASK | STATUS_FS_MASK | STATUS_VS_MASK | - STATUS_SPP_MASK | STATUS_SPIE_MASK | STATUS_UPIE_MASK | - STATUS_SIE_MASK | STATUS_UIE_MASK, - [RV64] = STATUS_SD_MASKS[RV64] | STATUS_UXL_MASK | STATUS_MXR_MASK | - STATUS_SUM_MASK | STATUS_XS_MASK | STATUS_FS_MASK | - STATUS_VS_MASK | STATUS_SPP_MASK | STATUS_SPIE_MASK | - STATUS_UPIE_MASK | STATUS_SIE_MASK | STATUS_UIE_MASK, +const RegVal MSTATUSH_MASKS[enums::Num_PrivilegeModeSet] = { + [enums::M] = STATUS_MBE_MASK[RV32], + [enums::MU] = STATUS_MBE_MASK[RV32], + [enums::MNU] = STATUS_MBE_MASK[RV32], + [enums::MSU] = STATUS_MBE_MASK[RV32] | STATUS_SBE_MASK[RV32], + [enums::MNSU] = STATUS_MBE_MASK[RV32] | STATUS_SBE_MASK[RV32], }; -const RegVal USTATUS_MASKS[enums::Num_RiscvType] = { - [RV32] = STATUS_SD_MASKS[RV32] | STATUS_MXR_MASK | STATUS_SUM_MASK | - STATUS_XS_MASK | STATUS_FS_MASK | STATUS_VS_MASK | - STATUS_UPIE_MASK | STATUS_UIE_MASK, - [RV64] = STATUS_SD_MASKS[RV64] | STATUS_MXR_MASK | STATUS_SUM_MASK | - STATUS_XS_MASK | STATUS_FS_MASK | STATUS_VS_MASK | - STATUS_UPIE_MASK | STATUS_UIE_MASK, +const RegVal +SSTATUS_MASKS[enums::Num_RiscvType][enums::Num_PrivilegeModeSet] = { + [RV32] = { + [enums::M] = 0ULL, + [enums::MU] = 0ULL, + [enums::MNU] = 0ULL, + [enums::MSU] = STATUS_SD_MASKS[RV32] | STATUS_MXR_MASK | + STATUS_SUM_MASK | + STATUS_XS_MASK | STATUS_FS_MASK | STATUS_VS_MASK | + STATUS_SPP_MASK | STATUS_SPIE_MASK | STATUS_SIE_MASK, + [enums::MNSU] = STATUS_SD_MASKS[RV32] | STATUS_MXR_MASK | + STATUS_SUM_MASK | + STATUS_XS_MASK | STATUS_FS_MASK | STATUS_VS_MASK | + STATUS_SPP_MASK | STATUS_SPIE_MASK | STATUS_UPIE_MASK | + STATUS_SIE_MASK | STATUS_UIE_MASK, + }, + [RV64] = { + [enums::M] = 0ULL, + [enums::MU] = 0ULL, + [enums::MNU] = 0ULL, + [enums::MSU] = STATUS_SD_MASKS[RV64] | STATUS_UXL_MASK | + STATUS_MXR_MASK | STATUS_SUM_MASK | + STATUS_XS_MASK | STATUS_FS_MASK | STATUS_VS_MASK | + STATUS_SPP_MASK | STATUS_SPIE_MASK | STATUS_SIE_MASK, + [enums::MNSU] = STATUS_SD_MASKS[RV64] | STATUS_UXL_MASK | + STATUS_MXR_MASK | STATUS_SUM_MASK | + STATUS_XS_MASK | STATUS_FS_MASK | STATUS_VS_MASK | + STATUS_SPP_MASK | STATUS_SPIE_MASK | + STATUS_UPIE_MASK | STATUS_SIE_MASK | STATUS_UIE_MASK, + }, +}; +const RegVal +USTATUS_MASKS[enums::Num_RiscvType][enums::Num_PrivilegeModeSet] = { + [RV32] = { + [enums::M] = 0ULL, + [enums::MU] = 0ULL, + [enums::MNU] = STATUS_SD_MASKS[RV32] | + STATUS_XS_MASK | STATUS_FS_MASK | STATUS_VS_MASK | + STATUS_UPIE_MASK | STATUS_UIE_MASK, + [enums::MSU] = 0ULL, + [enums::MNSU] = STATUS_SD_MASKS[RV32] | STATUS_MXR_MASK | + STATUS_SUM_MASK | + STATUS_XS_MASK | STATUS_FS_MASK | STATUS_VS_MASK | + STATUS_UPIE_MASK | STATUS_UIE_MASK, + }, + [RV64] = { + [enums::M] = 0ULL, + [enums::MU] = 0ULL, + [enums::MNU] = STATUS_SD_MASKS[RV64] | + STATUS_XS_MASK | STATUS_FS_MASK | STATUS_VS_MASK | + STATUS_UPIE_MASK | STATUS_UIE_MASK, + [enums::MSU] = 0ULL, + [enums::MNSU] = STATUS_SD_MASKS[RV64] | STATUS_MXR_MASK | + STATUS_SUM_MASK | + STATUS_XS_MASK | STATUS_FS_MASK | STATUS_VS_MASK | + STATUS_UPIE_MASK | STATUS_UIE_MASK, + }, }; const RegVal MEI_MASK = 1ULL << 11; @@ -1164,13 +1260,33 @@ const RegVal UTI_MASK = 1ULL << 4; const RegVal MSI_MASK = 1ULL << 3; const RegVal SSI_MASK = 1ULL << 1; const RegVal USI_MASK = 1ULL << 0; -const RegVal MI_MASK = MEI_MASK | SEI_MASK | UEI_MASK | - MTI_MASK | STI_MASK | UTI_MASK | - MSI_MASK | SSI_MASK | USI_MASK; -const RegVal SI_MASK = SEI_MASK | UEI_MASK | - STI_MASK | UTI_MASK | - SSI_MASK | USI_MASK; -const RegVal UI_MASK = UEI_MASK | UTI_MASK | USI_MASK; +const RegVal MI_MASK[enums::Num_PrivilegeModeSet] = { + [enums::M] = MEI_MASK| MTI_MASK | MSI_MASK, + [enums::MU] = MEI_MASK| MTI_MASK | MSI_MASK, + [enums::MNU] = MEI_MASK | UEI_MASK | MTI_MASK | UTI_MASK | + MSI_MASK | USI_MASK, + [enums::MSU] = MEI_MASK | SEI_MASK | MTI_MASK | STI_MASK | + MSI_MASK | SSI_MASK, + [enums::MNSU] = MEI_MASK | SEI_MASK | UEI_MASK | + MTI_MASK | STI_MASK | UTI_MASK | + MSI_MASK | SSI_MASK | USI_MASK, +}; +const RegVal SI_MASK[enums::Num_PrivilegeModeSet] = { + [enums::M] = 0ULL, + [enums::MU] = 0ULL, + [enums::MNU] = UEI_MASK | UTI_MASK | USI_MASK, + [enums::MSU] = SEI_MASK | STI_MASK | SSI_MASK, + [enums::MNSU] = SEI_MASK | UEI_MASK | + STI_MASK | UTI_MASK | + SSI_MASK | USI_MASK, +}; +const RegVal UI_MASK[enums::Num_PrivilegeModeSet] = { + [enums::M] = 0ULL, + [enums::MU] = 0ULL, + [enums::MNU] = UEI_MASK | UTI_MASK | USI_MASK, + [enums::MSU] = 0ULL, + [enums::MNSU] = UEI_MASK | UTI_MASK | USI_MASK, +}; const RegVal FFLAGS_MASK = (1 << FRM_OFFSET) - 1; const RegVal FRM_MASK = 0x7; @@ -1179,34 +1295,167 @@ const RegVal CAUSE_INTERRUPT_MASKS[enums::Num_RiscvType] = { [RV64] = (1ULL << 63), }; -const std::unordered_map CSRMasks[enums::Num_RiscvType] = { - [RV32] = {{CSR_USTATUS, USTATUS_MASKS[RV32]}, - {CSR_UIE, UI_MASK}, - {CSR_UIP, UI_MASK}, - {CSR_FFLAGS, FFLAGS_MASK}, - {CSR_FRM, FRM_MASK}, - {CSR_FCSR, FFLAGS_MASK | (FRM_MASK << FRM_OFFSET)}, - {CSR_SSTATUS, SSTATUS_MASKS[RV32]}, - {CSR_SIE, SI_MASK}, - {CSR_SIP, SI_MASK}, - {CSR_MSTATUS, MSTATUS_MASKS[RV32]}, - {CSR_MISA, MISA_MASKS[RV32]}, - {CSR_MIE, MI_MASK}, - {CSR_MSTATUSH, MSTATUSH_MASKS}, - {CSR_MIP, MI_MASK}}, - [RV64] = {{CSR_USTATUS, USTATUS_MASKS[RV64]}, - {CSR_UIE, UI_MASK}, - {CSR_UIP, UI_MASK}, - {CSR_FFLAGS, FFLAGS_MASK}, - {CSR_FRM, FRM_MASK}, - {CSR_FCSR, FFLAGS_MASK | (FRM_MASK << FRM_OFFSET)}, - {CSR_SSTATUS, SSTATUS_MASKS[RV64]}, - {CSR_SIE, SI_MASK}, - {CSR_SIP, SI_MASK}, - {CSR_MSTATUS, MSTATUS_MASKS[RV64]}, - {CSR_MISA, MISA_MASKS[RV64]}, - {CSR_MIE, MI_MASK}, - {CSR_MIP, MI_MASK}}, +const std::unordered_map +CSRMasks[enums::Num_RiscvType][enums::Num_PrivilegeModeSet] = { + [RV32] = { + [enums::M] = { + {CSR_USTATUS, USTATUS_MASKS[RV32][enums::M]}, + {CSR_UIE, UI_MASK[enums::M]}, + {CSR_UIP, UI_MASK[enums::M]}, + {CSR_FFLAGS, FFLAGS_MASK}, + {CSR_FRM, FRM_MASK}, + {CSR_FCSR, FFLAGS_MASK | (FRM_MASK << FRM_OFFSET)}, + {CSR_SSTATUS, SSTATUS_MASKS[RV32][enums::M]}, + {CSR_SIE, SI_MASK[enums::M]}, + {CSR_SIP, SI_MASK[enums::M]}, + {CSR_MSTATUS, MSTATUS_MASKS[RV32][enums::M]}, + {CSR_MISA, MISA_MASKS[RV32]}, + {CSR_MIE, MI_MASK[enums::M]}, + {CSR_MSTATUSH, MSTATUSH_MASKS[enums::M]}, + {CSR_MIP, MI_MASK[enums::M]}, + }, + [enums::MU] = { + {CSR_USTATUS, USTATUS_MASKS[RV32][enums::MU]}, + {CSR_UIE, UI_MASK[enums::MU]}, + {CSR_UIP, UI_MASK[enums::MU]}, + {CSR_FFLAGS, FFLAGS_MASK}, + {CSR_FRM, FRM_MASK}, + {CSR_FCSR, FFLAGS_MASK | (FRM_MASK << FRM_OFFSET)}, + {CSR_SSTATUS, SSTATUS_MASKS[RV32][enums::MU]}, + {CSR_SIE, SI_MASK[enums::MU]}, + {CSR_SIP, SI_MASK[enums::MU]}, + {CSR_MSTATUS, MSTATUS_MASKS[RV32][enums::MU]}, + {CSR_MISA, MISA_MASKS[RV32]}, + {CSR_MIE, MI_MASK[enums::MU]}, + {CSR_MSTATUSH, MSTATUSH_MASKS[enums::MU]}, + {CSR_MIP, MI_MASK[enums::MU]}, + }, + [enums::MNU] = { + {CSR_USTATUS, USTATUS_MASKS[RV32][enums::MNU]}, + {CSR_UIE, UI_MASK[enums::MNU]}, + {CSR_UIP, UI_MASK[enums::MNU]}, + {CSR_FFLAGS, FFLAGS_MASK}, + {CSR_FRM, FRM_MASK}, + {CSR_FCSR, FFLAGS_MASK | (FRM_MASK << FRM_OFFSET)}, + {CSR_SSTATUS, SSTATUS_MASKS[RV32][enums::MNU]}, + {CSR_SIE, SI_MASK[enums::MNU]}, + {CSR_SIP, SI_MASK[enums::MNU]}, + {CSR_MSTATUS, MSTATUS_MASKS[RV32][enums::MNU]}, + {CSR_MISA, MISA_MASKS[RV32]}, + {CSR_MIE, MI_MASK[enums::MNU]}, + {CSR_MSTATUSH, MSTATUSH_MASKS[enums::MNU]}, + {CSR_MIP, MI_MASK[enums::MNU]}, + }, + [enums::MSU] = { + {CSR_USTATUS, USTATUS_MASKS[RV32][enums::MSU]}, + {CSR_UIE, UI_MASK[enums::MSU]}, + {CSR_UIP, UI_MASK[enums::MSU]}, + {CSR_FFLAGS, FFLAGS_MASK}, + {CSR_FRM, FRM_MASK}, + {CSR_FCSR, FFLAGS_MASK | (FRM_MASK << FRM_OFFSET)}, + {CSR_SSTATUS, SSTATUS_MASKS[RV32][enums::MSU]}, + {CSR_SIE, SI_MASK[enums::MSU]}, + {CSR_SIP, SI_MASK[enums::MSU]}, + {CSR_MSTATUS, MSTATUS_MASKS[RV32][enums::MSU]}, + {CSR_MISA, MISA_MASKS[RV32]}, + {CSR_MIE, MI_MASK[enums::MSU]}, + {CSR_MSTATUSH, MSTATUSH_MASKS[enums::MSU]}, + {CSR_MIP, MI_MASK[enums::MSU]}, + }, + [enums::MNSU] = { + {CSR_USTATUS, USTATUS_MASKS[RV32][enums::MNSU]}, + {CSR_UIE, UI_MASK[enums::MNSU]}, + {CSR_UIP, UI_MASK[enums::MNSU]}, + {CSR_FFLAGS, FFLAGS_MASK}, + {CSR_FRM, FRM_MASK}, + {CSR_FCSR, FFLAGS_MASK | (FRM_MASK << FRM_OFFSET)}, + {CSR_SSTATUS, SSTATUS_MASKS[RV32][enums::MNSU]}, + {CSR_SIE, SI_MASK[enums::MNSU]}, + {CSR_SIP, SI_MASK[enums::MNSU]}, + {CSR_MSTATUS, MSTATUS_MASKS[RV32][enums::MNSU]}, + {CSR_MISA, MISA_MASKS[RV32]}, + {CSR_MIE, MI_MASK[enums::MNSU]}, + {CSR_MSTATUSH, MSTATUSH_MASKS[enums::MNSU]}, + {CSR_MIP, MI_MASK[enums::MNSU]}, + }, + }, + [RV64] = { + [enums::M] = { + {CSR_USTATUS, USTATUS_MASKS[RV64][enums::M]}, + {CSR_UIE, UI_MASK[enums::M]}, + {CSR_UIP, UI_MASK[enums::M]}, + {CSR_FFLAGS, FFLAGS_MASK}, + {CSR_FRM, FRM_MASK}, + {CSR_FCSR, FFLAGS_MASK | (FRM_MASK << FRM_OFFSET)}, + {CSR_SSTATUS, SSTATUS_MASKS[RV64][enums::M]}, + {CSR_SIE, SI_MASK[enums::M]}, + {CSR_SIP, SI_MASK[enums::M]}, + {CSR_MSTATUS, MSTATUS_MASKS[RV64][enums::M]}, + {CSR_MISA, MISA_MASKS[RV64]}, + {CSR_MIE, MI_MASK[enums::M]}, + {CSR_MIP, MI_MASK[enums::M]}, + }, + [enums::MU] = { + {CSR_USTATUS, USTATUS_MASKS[RV64][enums::MU]}, + {CSR_UIE, UI_MASK[enums::MU]}, + {CSR_UIP, UI_MASK[enums::MU]}, + {CSR_FFLAGS, FFLAGS_MASK}, + {CSR_FRM, FRM_MASK}, + {CSR_FCSR, FFLAGS_MASK | (FRM_MASK << FRM_OFFSET)}, + {CSR_SSTATUS, SSTATUS_MASKS[RV64][enums::MU]}, + {CSR_SIE, SI_MASK[enums::MU]}, + {CSR_SIP, SI_MASK[enums::MU]}, + {CSR_MSTATUS, MSTATUS_MASKS[RV64][enums::MU]}, + {CSR_MISA, MISA_MASKS[RV64]}, + {CSR_MIE, MI_MASK[enums::MU]}, + {CSR_MIP, MI_MASK[enums::MU]}, + }, + [enums::MNU] = { + {CSR_USTATUS, USTATUS_MASKS[RV64][enums::MNU]}, + {CSR_UIE, UI_MASK[enums::MNU]}, + {CSR_UIP, UI_MASK[enums::MNU]}, + {CSR_FFLAGS, FFLAGS_MASK}, + {CSR_FRM, FRM_MASK}, + {CSR_FCSR, FFLAGS_MASK | (FRM_MASK << FRM_OFFSET)}, + {CSR_SSTATUS, SSTATUS_MASKS[RV64][enums::MNU]}, + {CSR_SIE, SI_MASK[enums::MNU]}, + {CSR_SIP, SI_MASK[enums::MNU]}, + {CSR_MSTATUS, MSTATUS_MASKS[RV64][enums::MNU]}, + {CSR_MISA, MISA_MASKS[RV64]}, + {CSR_MIE, MI_MASK[enums::MNU]}, + {CSR_MIP, MI_MASK[enums::MNU]}, + }, + [enums::MSU] = { + {CSR_USTATUS, USTATUS_MASKS[RV64][enums::MSU]}, + {CSR_UIE, UI_MASK[enums::MSU]}, + {CSR_UIP, UI_MASK[enums::MSU]}, + {CSR_FFLAGS, FFLAGS_MASK}, + {CSR_FRM, FRM_MASK}, + {CSR_FCSR, FFLAGS_MASK | (FRM_MASK << FRM_OFFSET)}, + {CSR_SSTATUS, SSTATUS_MASKS[RV64][enums::MSU]}, + {CSR_SIE, SI_MASK[enums::MSU]}, + {CSR_SIP, SI_MASK[enums::MSU]}, + {CSR_MSTATUS, MSTATUS_MASKS[RV64][enums::MSU]}, + {CSR_MISA, MISA_MASKS[RV64]}, + {CSR_MIE, MI_MASK[enums::MSU]}, + {CSR_MIP, MI_MASK[enums::MSU]}, + }, + [enums::MNSU] = { + {CSR_USTATUS, USTATUS_MASKS[RV64][enums::MNSU]}, + {CSR_UIE, UI_MASK[enums::MNSU]}, + {CSR_UIP, UI_MASK[enums::MNSU]}, + {CSR_FFLAGS, FFLAGS_MASK}, + {CSR_FRM, FRM_MASK}, + {CSR_FCSR, FFLAGS_MASK | (FRM_MASK << FRM_OFFSET)}, + {CSR_SSTATUS, SSTATUS_MASKS[RV64][enums::MNSU]}, + {CSR_SIE, SI_MASK[enums::MNSU]}, + {CSR_SIP, SI_MASK[enums::MNSU]}, + {CSR_MSTATUS, MSTATUS_MASKS[RV64][enums::MNSU]}, + {CSR_MISA, MISA_MASKS[RV64]}, + {CSR_MIE, MI_MASK[enums::MNSU]}, + {CSR_MIP, MI_MASK[enums::MNSU]}, + }, + }, }; } // namespace RiscvISA diff --git a/src/arch/riscv/remote_gdb.cc b/src/arch/riscv/remote_gdb.cc index 48ce1d5d3b..df660d40d2 100644 --- a/src/arch/riscv/remote_gdb.cc +++ b/src/arch/riscv/remote_gdb.cc @@ -167,13 +167,22 @@ getRvType(ThreadContext* tc) return isa->rvType(); } +static PrivilegeModeSet +getPrivilegeModeSet(ThreadContext* tc) +{ + auto isa = dynamic_cast(tc->getIsaPtr()); + panic_if(!isa, "Cannot derive rv_type from non-riscv isa"); + return isa->getPrivilegeModeSet(); +} + template static void setRegNoEffectWithMask( - ThreadContext *context, RiscvType type, CSRIndex idx, xint val) + ThreadContext *context, RiscvType type, PrivilegeModeSet pms, + CSRIndex idx, xint val) { RegVal oldVal, newVal; - RegVal mask = CSRMasks[type].at(idx); + RegVal mask = CSRMasks[type][pms].at(idx); oldVal = context->readMiscRegNoEffect(CSRData.at(idx).physIndex); newVal = (oldVal & ~mask) | (val & mask); context->setMiscRegNoEffect(CSRData.at(idx).physIndex, newVal); @@ -181,10 +190,12 @@ setRegNoEffectWithMask( template static void -setRegWithMask(ThreadContext *context, RiscvType type, CSRIndex idx, xint val) +setRegWithMask( + ThreadContext *context, RiscvType type, PrivilegeModeSet pms, + CSRIndex idx, xint val) { RegVal oldVal, newVal; - RegVal mask = CSRMasks[type].at(idx); + RegVal mask = CSRMasks[type][pms].at(idx); oldVal = context->readMiscReg(CSRData.at(idx).physIndex); newVal = (oldVal & ~mask) | (val & mask); context->setMiscReg(CSRData.at(idx).physIndex, newVal); @@ -225,7 +236,8 @@ void RemoteGDB::Riscv32GdbRegCache::getRegs(ThreadContext *context) { DPRINTF(GDBAcc, "getregs in remotegdb, size %lu\n", size()); - auto& RVxCSRMasks = CSRMasks[RV32]; + PrivilegeModeSet pms = getPrivilegeModeSet(context); + auto& RVxCSRMasks = CSRMasks[RV32][pms]; // General registers for (int i = 0; i < int_reg::NumArchRegs; i++) { @@ -339,6 +351,7 @@ void RemoteGDB::Riscv32GdbRegCache::setRegs(ThreadContext *context) const { DPRINTF(GDBAcc, "setregs in remotegdb \n"); + PrivilegeModeSet pms = getPrivilegeModeSet(context); for (int i = 0; i < int_reg::NumArchRegs; i++) context->setReg(intRegClass[i], r.gpr[i]); context->pcState(r.pc); @@ -347,16 +360,16 @@ RemoteGDB::Riscv32GdbRegCache::setRegs(ThreadContext *context) const for (int i = 0; i < float_reg::NumRegs; i++) context->setReg(floatRegClass[i], r.fpu[i]); - setRegNoEffectWithMask(context, RV32, CSR_FFLAGS, r.fflags); - setRegNoEffectWithMask(context, RV32, CSR_FRM, r.frm); - setRegNoEffectWithMask(context, RV32, CSR_FCSR, r.fcsr); + setRegNoEffectWithMask(context, RV32, pms, CSR_FFLAGS, r.fflags); + setRegNoEffectWithMask(context, RV32, pms, CSR_FRM, r.frm); + setRegNoEffectWithMask(context, RV32, pms, CSR_FCSR, r.fcsr); // TODO: implement CSR counter registers for mcycle(h), minstret(h) // U mode CSR - setRegNoEffectWithMask(context, RV32, CSR_USTATUS, r.ustatus); - setRegWithMask(context, RV32, CSR_UIE, r.uie); - setRegWithMask(context, RV32, CSR_UIP, r.uip); + setRegNoEffectWithMask(context, RV32, pms, CSR_USTATUS, r.ustatus); + setRegWithMask(context, RV32, pms, CSR_UIE, r.uie); + setRegWithMask(context, RV32, pms, CSR_UIP, r.uip); context->setMiscRegNoEffect( CSRData.at(CSR_UTVEC).physIndex, r.utvec); context->setMiscRegNoEffect( @@ -369,9 +382,9 @@ RemoteGDB::Riscv32GdbRegCache::setRegs(ThreadContext *context) const CSRData.at(CSR_UTVAL).physIndex, r.utval); // S mode CSR - setRegNoEffectWithMask(context, RV32, CSR_SSTATUS, r.sstatus); - setRegWithMask(context, RV32, CSR_SIE, r.sie); - setRegWithMask(context, RV32, CSR_SIP, r.sip); + setRegNoEffectWithMask(context, RV32, pms, CSR_SSTATUS, r.sstatus); + setRegWithMask(context, RV32, pms, CSR_SIE, r.sie); + setRegWithMask(context, RV32, pms, CSR_SIP, r.sip); context->setMiscRegNoEffect( CSRData.at(CSR_SEDELEG).physIndex, r.sedeleg); context->setMiscRegNoEffect( @@ -392,10 +405,10 @@ RemoteGDB::Riscv32GdbRegCache::setRegs(ThreadContext *context) const CSRData.at(CSR_SATP).physIndex, r.satp); // M mode CSR - setRegNoEffectWithMask(context, RV32, CSR_MSTATUS, r.mstatus); - setRegNoEffectWithMask(context, RV32, CSR_MISA, r.misa); - setRegWithMask(context, RV32, CSR_MIE, r.mie); - setRegWithMask(context, RV32, CSR_MIP, r.mip); + setRegNoEffectWithMask(context, RV32, pms, CSR_MSTATUS, r.mstatus); + setRegNoEffectWithMask(context, RV32, pms, CSR_MISA, r.misa); + setRegWithMask(context, RV32, pms, CSR_MIE, r.mie); + setRegWithMask(context, RV32, pms, CSR_MIP, r.mip); context->setMiscRegNoEffect( CSRData.at(CSR_MEDELEG).physIndex, r.medeleg); context->setMiscRegNoEffect( @@ -420,7 +433,8 @@ void RemoteGDB::Riscv64GdbRegCache::getRegs(ThreadContext *context) { DPRINTF(GDBAcc, "getregs in remotegdb, size %lu\n", size()); - auto& RVxCSRMasks = CSRMasks[RV64]; + PrivilegeModeSet pms = getPrivilegeModeSet(context); + auto& RVxCSRMasks = CSRMasks[RV64][pms]; // General registers for (int i = 0; i < int_reg::NumArchRegs; i++) { @@ -528,6 +542,7 @@ void RemoteGDB::Riscv64GdbRegCache::setRegs(ThreadContext *context) const { DPRINTF(GDBAcc, "setregs in remotegdb \n"); + PrivilegeModeSet pms = getPrivilegeModeSet(context); for (int i = 0; i < int_reg::NumArchRegs; i++) context->setReg(intRegClass[i], r.gpr[i]); context->pcState(r.pc); @@ -536,16 +551,16 @@ RemoteGDB::Riscv64GdbRegCache::setRegs(ThreadContext *context) const for (int i = 0; i < float_reg::NumRegs; i++) context->setReg(floatRegClass[i], r.fpu[i]); - setRegNoEffectWithMask(context, RV64, CSR_FFLAGS, r.fflags); - setRegNoEffectWithMask(context, RV64, CSR_FRM, r.frm); - setRegNoEffectWithMask(context, RV64, CSR_FCSR, r.fcsr); + setRegNoEffectWithMask(context, RV64, pms, CSR_FFLAGS, r.fflags); + setRegNoEffectWithMask(context, RV64, pms, CSR_FRM, r.frm); + setRegNoEffectWithMask(context, RV64, pms, CSR_FCSR, r.fcsr); // TODO: implement CSR counter registers for mcycle, minstret // U mode CSR - setRegNoEffectWithMask(context, RV64, CSR_USTATUS, r.ustatus); - setRegWithMask(context, RV64, CSR_UIE, r.uie); - setRegWithMask(context, RV64, CSR_UIP, r.uip); + setRegNoEffectWithMask(context, RV64, pms, CSR_USTATUS, r.ustatus); + setRegWithMask(context, RV64, pms, CSR_UIE, r.uie); + setRegWithMask(context, RV64, pms, CSR_UIP, r.uip); context->setMiscRegNoEffect( CSRData.at(CSR_UTVEC).physIndex, r.utvec); context->setMiscRegNoEffect( @@ -558,9 +573,10 @@ RemoteGDB::Riscv64GdbRegCache::setRegs(ThreadContext *context) const CSRData.at(CSR_UTVAL).physIndex, r.utval); // S mode CSR - setRegNoEffectWithMask(context, RV64, CSR_SSTATUS, r.sstatus); - setRegWithMask(context, RV64, CSR_SIE, r.sie); - setRegWithMask(context, RV64, CSR_SIP, r.sip); + setRegNoEffectWithMask( + context, RV64, pms, CSR_SSTATUS, r.sstatus); + setRegWithMask(context, RV64, pms, CSR_SIE, r.sie); + setRegWithMask(context, RV64, pms, CSR_SIP, r.sip); context->setMiscRegNoEffect( CSRData.at(CSR_SEDELEG).physIndex, r.sedeleg); context->setMiscRegNoEffect( @@ -581,10 +597,11 @@ RemoteGDB::Riscv64GdbRegCache::setRegs(ThreadContext *context) const CSRData.at(CSR_SATP).physIndex, r.satp); // M mode CSR - setRegNoEffectWithMask(context, RV64, CSR_MSTATUS, r.mstatus); - setRegNoEffectWithMask(context, RV64, CSR_MISA, r.misa); - setRegWithMask(context, RV64, CSR_MIE, r.mie); - setRegWithMask(context, RV64, CSR_MIP, r.mip); + setRegNoEffectWithMask( + context, RV64, pms, CSR_MSTATUS, r.mstatus); + setRegNoEffectWithMask(context, RV64, pms, CSR_MISA, r.misa); + setRegWithMask(context, RV64, pms, CSR_MIE, r.mie); + setRegWithMask(context, RV64, pms, CSR_MIP, r.mip); context->setMiscRegNoEffect( CSRData.at(CSR_MEDELEG).physIndex, r.medeleg); context->setMiscRegNoEffect(