Registers: Eliminate the ISA defined floating point register file.
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@@ -265,7 +265,7 @@ InOrderCPU::InOrderCPU(Params *params)
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lastSquashCycle[tid] = 0;
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intRegFile[tid].clear();
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floatRegFile[tid].clear();
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memset(floatRegs.i[tid], 0, sizeof(floatRegs.i[tid]));
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isa[tid].clear();
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isa[tid].expandForMultithreading(numThreads, numVirtProcs);
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@@ -892,13 +892,13 @@ InOrderCPU::readIntReg(int reg_idx, ThreadID tid)
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FloatReg
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InOrderCPU::readFloatReg(int reg_idx, ThreadID tid)
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{
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return floatRegFile[tid].readReg(reg_idx);
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return floatRegs.f[tid][reg_idx];
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}
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FloatRegBits
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InOrderCPU::readFloatRegBits(int reg_idx, ThreadID tid)
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{;
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return floatRegFile[tid].readRegBits(reg_idx);
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return floatRegs.i[tid][reg_idx];
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}
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void
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@@ -911,14 +911,14 @@ InOrderCPU::setIntReg(int reg_idx, uint64_t val, ThreadID tid)
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void
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InOrderCPU::setFloatReg(int reg_idx, FloatReg val, ThreadID tid)
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{
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floatRegFile[tid].setReg(reg_idx, val);
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floatRegs.f[tid][reg_idx] = val;
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}
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void
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InOrderCPU::setFloatRegBits(int reg_idx, FloatRegBits val, ThreadID tid)
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{
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floatRegFile[tid].setRegBits(reg_idx, val);
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floatRegs.i[tid][reg_idx] = val;
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}
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uint64_t
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@@ -259,7 +259,10 @@ class InOrderCPU : public BaseCPU
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/** The Register File for the CPU */
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TheISA::IntRegFile intRegFile[ThePipeline::MaxThreads];;
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TheISA::FloatRegFile floatRegFile[ThePipeline::MaxThreads];;
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union {
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FloatReg f[ThePipeline::MaxThreads][TheISA::NumFloatRegs];
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FloatRegBits i[ThePipeline::MaxThreads][TheISA::NumFloatRegs];
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} floatRegs;
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/** ISA state */
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TheISA::ISA isa[ThePipeline::MaxThreads];
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