Registers: Eliminate the ISA defined floating point register file.

src/cpu/inorder/cpu.cc

@@ -265,7 +265,7 @@ InOrderCPU::InOrderCPU(Params *params)
         lastSquashCycle[tid] = 0;
 
         intRegFile[tid].clear();
-        floatRegFile[tid].clear();
+        memset(floatRegs.i[tid], 0, sizeof(floatRegs.i[tid]));
         isa[tid].clear();
 
         isa[tid].expandForMultithreading(numThreads, numVirtProcs);
@@ -892,13 +892,13 @@ InOrderCPU::readIntReg(int reg_idx, ThreadID tid)
 FloatReg
 InOrderCPU::readFloatReg(int reg_idx, ThreadID tid)
 {
-    return floatRegFile[tid].readReg(reg_idx);
+    return floatRegs.f[tid][reg_idx];
 }
 
 FloatRegBits
 InOrderCPU::readFloatRegBits(int reg_idx, ThreadID tid)
 {;
-    return floatRegFile[tid].readRegBits(reg_idx);
+    return floatRegs.i[tid][reg_idx];
 }
 
 void
@@ -911,14 +911,14 @@ InOrderCPU::setIntReg(int reg_idx, uint64_t val, ThreadID tid)
 void
 InOrderCPU::setFloatReg(int reg_idx, FloatReg val, ThreadID tid)
 {
-    floatRegFile[tid].setReg(reg_idx, val);
+    floatRegs.f[tid][reg_idx] = val;
 }
 
 
 void
 InOrderCPU::setFloatRegBits(int reg_idx, FloatRegBits val, ThreadID tid)
 {
-    floatRegFile[tid].setRegBits(reg_idx, val);
+    floatRegs.i[tid][reg_idx] = val;
 }
 
 uint64_t

src/cpu/inorder/cpu.hh

@@ -259,7 +259,10 @@ class InOrderCPU : public BaseCPU
 
     /** The Register File for the CPU */
     TheISA::IntRegFile intRegFile[ThePipeline::MaxThreads];;
-    TheISA::FloatRegFile floatRegFile[ThePipeline::MaxThreads];;
+    union {
+        FloatReg f[ThePipeline::MaxThreads][TheISA::NumFloatRegs];
+        FloatRegBits i[ThePipeline::MaxThreads][TheISA::NumFloatRegs];
+    } floatRegs;
 
     /** ISA state */
     TheISA::ISA isa[ThePipeline::MaxThreads];

src/cpu/simple_thread.cc

@@ -192,6 +192,7 @@ SimpleThread::serialize(ostream &os)
 {
     ThreadState::serialize(os);
     regs.serialize(cpu, os);
+    SERIALIZE_ARRAY(floatRegs.i, TheISA::NumFloatRegs);
     // thread_num and cpu_id are deterministic from the config
 }
 
@@ -201,6 +202,7 @@ SimpleThread::unserialize(Checkpoint *cp, const std::string &section)
 {
     ThreadState::unserialize(cp, section);
     regs.unserialize(cpu, cp, section);
+    UNSERIALIZE_ARRAY(floatRegs.i, TheISA::NumFloatRegs);
     // thread_num and cpu_id are deterministic from the config
 }
 

src/cpu/simple_thread.hh

@@ -99,6 +99,10 @@ class SimpleThread : public ThreadState
 
   protected:
     RegFile regs;       // correct-path register context
+    union {
+        FloatReg f[TheISA::NumFloatRegs];
+        FloatRegBits i[TheISA::NumFloatRegs];
+    } floatRegs;
     TheISA::ISA isa;    // one "instance" of the current ISA.
 
   public:
@@ -223,7 +227,11 @@ class SimpleThread : public ThreadState
 
     void copyArchRegs(ThreadContext *tc);
 
-    void clearArchRegs() { regs.clear(); }
+    void clearArchRegs()
+    {
+        regs.clear();
+        memset(floatRegs.i, 0, sizeof(floatRegs.i));
+    }
 
     //
     // New accessors for new decoder.
@@ -237,13 +245,13 @@ class SimpleThread : public ThreadState
     FloatReg readFloatReg(int reg_idx)
     {
         int flatIndex = isa.flattenFloatIndex(reg_idx);
-        return regs.readFloatReg(flatIndex);
+        return floatRegs.f[flatIndex];
     }
 
     FloatRegBits readFloatRegBits(int reg_idx)
     {
         int flatIndex = isa.flattenFloatIndex(reg_idx);
-        return regs.readFloatRegBits(flatIndex);
+        return floatRegs.i[flatIndex];
     }
 
     void setIntReg(int reg_idx, uint64_t val)
@@ -255,13 +263,13 @@ class SimpleThread : public ThreadState
     void setFloatReg(int reg_idx, FloatReg val)
     {
         int flatIndex = isa.flattenFloatIndex(reg_idx);
-        regs.setFloatReg(flatIndex, val);
+        floatRegs.f[flatIndex] = val;
     }
 
     void setFloatRegBits(int reg_idx, FloatRegBits val)
     {
         int flatIndex = isa.flattenFloatIndex(reg_idx);
-        regs.setFloatRegBits(flatIndex, val);
+        floatRegs.i[flatIndex] = val;
     }
 
     uint64_t readPC()