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style: eliminate equality tests with true and false

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Using '== true' in a boolean expression is totally redundant,
and using '== false' is pretty verbose (and arguably less
readable in most cases) compared to '!'.

It's somewhat of a pet peeve, perhaps, but I had some time
waiting for some tests to run and decided to clean these up.

Unfortunately, SLICC appears not to have the '!' operator,
so I had to leave the '== false' tests in the SLICC code.
This commit is contained in:
Steve Reinhardt
2014-05-31 18:00:23 -07:00
parent 2a8088f5ae
commit 0be64ffe2f
24 changed files with 49 additions and 50 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/cpu/exetrace.cc
View File

@@ -115,7 +115,7 @@ Trace::ExeTracerRecord::traceInst(StaticInstPtr inst, bool ran)
outs << Enums::OpClassStrings[inst->opClass()] << " : ";
}
if (Debug::ExecResult && predicate == false) {
if (Debug::ExecResult && !predicate) {
outs << "Predicated False";
}

2
src/cpu/inorder/cpu.cc
View File

@@ -1763,7 +1763,7 @@ InOrderCPU::cleanUpRemovedInsts()
// Clear if Non-Speculative
if (inst->staticInst &&
inst->seqNum == nonSpecSeqNum[tid] &&
nonSpecInstActive[tid] == true) {
nonSpecInstActive[tid]) {
nonSpecInstActive[tid] = false;
}

6
src/cpu/inorder/pipeline_stage.cc
View File

@@ -248,19 +248,19 @@ void
PipelineStage::removeStalls(ThreadID tid)
{
for (int st_num = 0; st_num < NumStages; st_num++) {
if (stalls[tid].stage[st_num] == true) {
if (stalls[tid].stage[st_num]) {
DPRINTF(InOrderStage, "Removing stall from stage %i.\n",
st_num);
stalls[tid].stage[st_num] = false;
}
if (toPrevStages->stageBlock[st_num][tid] == true) {
if (toPrevStages->stageBlock[st_num][tid]) {
DPRINTF(InOrderStage, "Removing pending block from stage %i.\n",
st_num);
toPrevStages->stageBlock[st_num][tid] = false;
}
if (fromNextStages->stageBlock[st_num][tid] == true) {
if (fromNextStages->stageBlock[st_num][tid]) {
DPRINTF(InOrderStage, "Removing pending block from stage %i.\n",
st_num);
fromNextStages->stageBlock[st_num][tid] = false;

2
src/cpu/inorder/resources/use_def.cc
View File

@@ -191,7 +191,7 @@ UseDefUnit::execute(int slot_idx)
// If there is a non-speculative instruction
// in the pipeline then stall instructions here
// ---
if (*nonSpecInstActive[tid] == true && seq_num > *nonSpecSeqNum[tid]) {
if (*nonSpecInstActive[tid] && seq_num > *nonSpecSeqNum[tid]) {
DPRINTF(InOrderUseDef, "[tid:%i]: [sn:%i] cannot execute because"
"there is non-speculative instruction [sn:%i] has not "
"graduated.\n", tid, seq_num, *nonSpecSeqNum[tid]);

6
src/cpu/o3/commit_impl.hh
View File

@@ -843,10 +843,10 @@ DefaultCommit<Impl>::commit()
// Not sure which one takes priority. I think if we have
// both, that's a bad sign.
if (trapSquash[tid] == true) {
if (trapSquash[tid]) {
assert(!tcSquash[tid]);
squashFromTrap(tid);
} else if (tcSquash[tid] == true) {
} else if (tcSquash[tid]) {
assert(commitStatus[tid] != TrapPending);
squashFromTC(tid);
} else if (commitStatus[tid] == SquashAfterPending) {
@@ -885,7 +885,7 @@ DefaultCommit<Impl>::commit()
// then use one older sequence number.
InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid];
if (fromIEW->includeSquashInst[tid] == true) {
if (fromIEW->includeSquashInst[tid]) {
squashed_inst--;
}

4
src/cpu/o3/fetch_impl.hh
View File

@@ -430,8 +430,8 @@ DefaultFetch<Impl>::drainSanityCheck() const
assert(isDrained());
assert(retryPkt == NULL);
assert(retryTid == InvalidThreadID);
assert(cacheBlocked == false);
assert(interruptPending == false);
assert(!cacheBlocked);
assert(!interruptPending);
for (ThreadID i = 0; i < numThreads; ++i) {
assert(!memReq[i]);

10
src/cpu/o3/iew_impl.hh
View File

@@ -487,7 +487,7 @@ DefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, ThreadID tid)
DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %s "
"[sn:%i].\n", tid, inst->pcState(), inst->seqNum);
if (toCommit->squash[tid] == false ||
if (!toCommit->squash[tid] ||
inst->seqNum < toCommit->squashedSeqNum[tid]) {
toCommit->squash[tid] = true;
toCommit->squashedSeqNum[tid] = inst->seqNum;
@@ -517,7 +517,7 @@ DefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, ThreadID tid)
// case the memory violator should take precedence over the branch
// misprediction because it requires the violator itself to be included in
// the squash.
if (toCommit->squash[tid] == false ||
if (!toCommit->squash[tid] ||
inst->seqNum <= toCommit->squashedSeqNum[tid]) {
toCommit->squash[tid] = true;
@@ -538,7 +538,7 @@ DefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, ThreadID tid)
{
DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, "
"PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum);
if (toCommit->squash[tid] == false ||
if (!toCommit->squash[tid] ||
inst->seqNum < toCommit->squashedSeqNum[tid]) {
toCommit->squash[tid] = true;
@@ -1314,7 +1314,7 @@ DefaultIEW<Impl>::executeInsts()
}
// If the store had a fault then it may not have a mem req
if (fault != NoFault || inst->readPredicate() == false ||
if (fault != NoFault || !inst->readPredicate() ||
!inst->isStoreConditional()) {
// If the instruction faulted, then we need to send it along
// to commit without the instruction completing.
@@ -1339,7 +1339,7 @@ DefaultIEW<Impl>::executeInsts()
// will be replaced and we will lose it.
if (inst->getFault() == NoFault) {
inst->execute();
if (inst->readPredicate() == false)
if (!inst->readPredicate())
inst->forwardOldRegs();
}

2
src/cpu/o3/inst_queue_impl.hh
View File

@@ -1262,7 +1262,7 @@ InstructionQueue<Impl>::addToDependents(DynInstPtr &new_inst)
// it be added to the dependency graph.
if (src_reg >= numPhysRegs) {
continue;
} else if (regScoreboard[src_reg] == false) {
} else if (!regScoreboard[src_reg]) {
DPRINTF(IQ, "Instruction PC %s has src reg %i that "
"is being added to the dependency chain.\n",
new_inst->pcState(), src_reg);

8
src/cpu/o3/lsq_unit_impl.hh
View File

@@ -612,12 +612,12 @@ LSQUnit<Impl>::executeLoad(DynInstPtr &inst)
// If the instruction faulted or predicated false, then we need to send it
// along to commit without the instruction completing.
if (load_fault != NoFault || inst->readPredicate() == false) {
if (load_fault != NoFault || !inst->readPredicate()) {
// Send this instruction to commit, also make sure iew stage
// realizes there is activity.
// Mark it as executed unless it is an uncached load that
// needs to hit the head of commit.
if (inst->readPredicate() == false)
if (!inst->readPredicate())
inst->forwardOldRegs();
DPRINTF(LSQUnit, "Load [sn:%lli] not executed from %s\n",
inst->seqNum,
@@ -665,7 +665,7 @@ LSQUnit<Impl>::executeStore(DynInstPtr &store_inst)
store_fault == NoFault)
return store_fault;
if (store_inst->readPredicate() == false)
if (!store_inst->readPredicate())
store_inst->forwardOldRegs();
if (storeQueue[store_idx].size == 0) {
@@ -673,7 +673,7 @@ LSQUnit<Impl>::executeStore(DynInstPtr &store_inst)
store_inst->pcState(), store_inst->seqNum);
return store_fault;
} else if (store_inst->readPredicate() == false) {
} else if (!store_inst->readPredicate()) {
DPRINTF(LSQUnit, "Store [sn:%lli] not executed from predication\n",
store_inst->seqNum);
return store_fault;

2
src/cpu/o3/rob_impl.hh
View File

@@ -519,7 +519,7 @@ ROB<Impl>::readHeadInst(ThreadID tid)
if (threadEntries[tid] != 0) {
InstIt head_thread = instList[tid].begin();
assert((*head_thread)->isInROB()==true);
assert((*head_thread)->isInROB());
return *head_thread;
} else {

2
src/cpu/ozone/inst_queue_impl.hh
View File

@@ -1101,7 +1101,7 @@ InstQueue<Impl>::addToDependents(DynInstPtr &new_inst)
// it be added to the dependency graph.
if (src_reg >= numPhysRegs) {
continue;
} else if (regScoreboard[src_reg] == false) {
} else if (!regScoreboard[src_reg]) {
DPRINTF(IQ, "Instruction PC %#x has src reg %i that "
"is being added to the dependency chain.\n",
new_inst->readPC(), src_reg);