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cpu: Consolidate and move the CPU's calls to TheISA::initCPU.

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TheISA::initCPU is basically an ISA specific implementation of reset
logic on architectural state. As such, it only needs to be called if
we're not going to load a checkpoint, ie in initState.

Also, since the implementation was the same across all CPUs, this
change collapses all the individual implementations down into the base
CPU class.

Change-Id: Id68133fd7f31619c90bf7b3aad35ae20871acaa4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24189
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
This commit is contained in:
Gabe Black
2020-01-09 02:10:15 -08:00
parent ae7dd927e2
commit 0b8d02dec4
6 changed files with 10 additions and 27 deletions
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9
src/cpu/base.cc
View File

@@ -320,6 +320,15 @@ BaseCPU::init()
} }
} }
void
BaseCPU::initState()
{
if (FullSystem && !params()->switched_out) {
for (auto *tc: threadContexts)
TheISA::initCPU(tc, tc->contextId());
}
}
void void
BaseCPU::startup() BaseCPU::startup()
{ {

1
src/cpu/base.hh
View File

@@ -314,6 +314,7 @@ class BaseCPU : public ClockedObject
virtual ~BaseCPU(); virtual ~BaseCPU();
void init() override; void init() override;
void initState() override;
void startup() override; void startup() override;
void regStats() override; void regStats() override;

4
src/cpu/kvm/base.cc
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@@ -114,10 +114,6 @@ BaseKvmCPU::init()
fatal("KVM: Multithreading not supported"); fatal("KVM: Multithreading not supported");
tc->initMemProxies(tc); tc->initMemProxies(tc);
// initialize CPU, including PC
if (FullSystem && !switchedOut())
TheISA::initCPU(tc, tc->contextId());
} }
void void

11
src/cpu/minor/cpu.cc
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@@ -108,17 +108,6 @@ MinorCPU::init()
tc->initMemProxies(tc); tc->initMemProxies(tc);
} }
/* Initialise CPUs (== threads in the ISA) */
if (FullSystem && !params()->switched_out) {
for (ThreadID thread_id = 0; thread_id < threads.size(); thread_id++)
{
ThreadContext *tc = getContext(thread_id);
/* Initialize CPU, including PC */
TheISA::initCPU(tc, cpuId());
}
}
} }
/** Stats interface from SimObject (by way of BaseCPU) */ /** Stats interface from SimObject (by way of BaseCPU) */

7
src/cpu/o3/cpu.cc
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@@ -599,13 +599,6 @@ FullO3CPU<Impl>::init()
thread[tid]->initMemProxies(thread[tid]->getTC()); thread[tid]->initMemProxies(thread[tid]->getTC());
} }
if (FullSystem && !params()->switched_out) {
for (ThreadID tid = 0; tid < numThreads; tid++) {
ThreadContext *src_tc = threadContexts[tid];
TheISA::initCPU(src_tc, src_tc->contextId());
}
}
// Clear noSquashFromTC. // Clear noSquashFromTC.
for (int tid = 0; tid < numThreads; ++tid) for (int tid = 0; tid < numThreads; ++tid)
thread[tid]->noSquashFromTC = false; thread[tid]->noSquashFromTC = false;

5
src/cpu/simple/base.cc
View File

@@ -130,11 +130,6 @@ BaseSimpleCPU::init()
for (auto tc : threadContexts) { for (auto tc : threadContexts) {
// Initialise the ThreadContext's memory proxies // Initialise the ThreadContext's memory proxies
tc->initMemProxies(tc); tc->initMemProxies(tc);
if (FullSystem && !params()->switched_out) {
// initialize CPU, including PC
TheISA::initCPU(tc, tc->contextId());
}
} }
} }