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Merge zizzer.eecs.umich.edu:/bk/newmem

Browse Source 
into  zeep.eecs.umich.edu:/home/gblack/m5/newmem

--HG--
extra : convert_revision : 2711fec2bf72801999b060e65f0bf744c18734fb
This commit is contained in:
Gabe Black
2006-10-20 16:39:47 -04:00
parent 76c07ea46b 6c6b78126a
commit 0b5cf4ba6e
130 changed files with 1608 additions and 1485 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
src/cpu/checker/cpu.cc
View File

@@ -34,10 +34,8 @@
#include "cpu/base.hh"
#include "cpu/checker/cpu.hh"
#include "cpu/simple_thread.hh"
#include "cpu/thread_context.hh"
#include "cpu/static_inst.hh"
#include "mem/packet_impl.hh"
#include "sim/byteswap.hh"
#include "cpu/thread_context.hh"
#if FULL_SYSTEM
#include "arch/vtophys.hh"
@@ -171,7 +169,7 @@ CheckerCPU::read(Addr addr, T &data, unsigned flags)
// translate to physical address
translateDataReadReq(memReq);
Packet *pkt = new Packet(memReq, Packet::ReadReq, Packet::Broadcast);
PacketPtr pkt = new Packet(memReq, Packet::ReadReq, Packet::Broadcast);
pkt->dataStatic(&data);
@@ -258,7 +256,7 @@ CheckerCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
T inst_data;
/*
// This code would work if the LSQ allowed for snooping.
Packet *pkt = new Packet(memReq, Packet::ReadReq, Packet::Broadcast);
PacketPtr pkt = new Packet(memReq, Packet::ReadReq, Packet::Broadcast);
pkt.dataStatic(&inst_data);
dcachePort->sendFunctional(pkt);

4
src/cpu/checker/cpu_impl.hh
View File

@@ -37,8 +37,6 @@
#include "cpu/simple_thread.hh"
#include "cpu/thread_context.hh"
#include "cpu/static_inst.hh"
#include "mem/packet_impl.hh"
#include "sim/byteswap.hh"
#include "sim/sim_object.hh"
#include "sim/stats.hh"
@@ -183,7 +181,7 @@ Checker<DynInstPtr>::verify(DynInstPtr &completed_inst)
}
if (fault == NoFault) {
Packet *pkt = new Packet(memReq, Packet::ReadReq,
PacketPtr pkt = new Packet(memReq, Packet::ReadReq,
Packet::Broadcast);
pkt->dataStatic(&machInst);

44
src/cpu/memtest/memtest.cc
View File

@@ -38,42 +38,42 @@
#include "base/misc.hh"
#include "base/statistics.hh"
//#include "cpu/simple_thread.hh"
#include "cpu/memtest/memtest.hh"
//#include "cpu/simple_thread.hh"
//#include "mem/cache/base_cache.hh"
#include "mem/mem_object.hh"
#include "mem/port.hh"
#include "mem/packet.hh"
//#include "mem/physical.hh"
#include "mem/request.hh"
#include "sim/builder.hh"
#include "sim/sim_events.hh"
#include "sim/stats.hh"
#include "mem/packet.hh"
#include "mem/request.hh"
#include "mem/port.hh"
#include "mem/mem_object.hh"
using namespace std;
int TESTER_ALLOCATOR=0;
bool
MemTest::CpuPort::recvTiming(Packet *pkt)
MemTest::CpuPort::recvTiming(PacketPtr pkt)
{
memtest->completeRequest(pkt);
return true;
}
Tick
MemTest::CpuPort::recvAtomic(Packet *pkt)
MemTest::CpuPort::recvAtomic(PacketPtr pkt)
{
panic("MemTest doesn't expect recvAtomic callback!");
return curTick;
}
void
MemTest::CpuPort::recvFunctional(Packet *pkt)
MemTest::CpuPort::recvFunctional(PacketPtr pkt)
{
//Do nothing if we see one come through
if (curTick != 0)//Supress warning durring initialization
warn("Functional Writes not implemented in MemTester\n");
// if (curTick != 0)//Supress warning durring initialization
// warn("Functional Writes not implemented in MemTester\n");
//Need to find any response values that intersect and update
return;
}
@@ -94,7 +94,7 @@ MemTest::CpuPort::recvRetry()
}
void
MemTest::sendPkt(Packet *pkt) {
MemTest::sendPkt(PacketPtr pkt) {
if (atomic) {
cachePort.sendAtomic(pkt);
pkt->makeAtomicResponse();
@@ -113,7 +113,7 @@ MemTest::MemTest(const string &name,
// PhysicalMemory *check_mem,
unsigned _memorySize,
unsigned _percentReads,
// unsigned _percentCopies,
unsigned _percentFunctional,
unsigned _percentUncacheable,
unsigned _progressInterval,
unsigned _percentSourceUnaligned,
@@ -130,7 +130,7 @@ MemTest::MemTest(const string &name,
// checkMem(check_mem),
size(_memorySize),
percentReads(_percentReads),
// percentCopies(_percentCopies),
percentFunctional(_percentFunctional),
percentUncacheable(_percentUncacheable),
progressInterval(_progressInterval),
nextProgressMessage(_progressInterval),
@@ -204,7 +204,7 @@ printData(ostream &os, uint8_t *data, int nbytes)
}
void
MemTest::completeRequest(Packet *pkt)
MemTest::completeRequest(PacketPtr pkt)
{
MemTestSenderState *state =
dynamic_cast<MemTestSenderState *>(pkt->senderState);
@@ -345,8 +345,8 @@ MemTest::tick()
} else {
paddr = ((base) ? baseAddr1 : baseAddr2) + offset;
}
//bool probe = (random() % 2 == 1) && !req->isUncacheable();
bool probe = false;
bool probe = (random() % 100 < percentFunctional) && !(flags & UNCACHEABLE);
//bool probe = false;
paddr &= ~((1 << access_size) - 1);
req->setPhys(paddr, 1 << access_size, flags);
@@ -381,13 +381,14 @@ MemTest::tick()
<< dec << curTick << endl;
}
Packet *pkt = new Packet(req, Packet::ReadReq, Packet::Broadcast);
PacketPtr pkt = new Packet(req, Packet::ReadReq, Packet::Broadcast);
pkt->dataDynamicArray(new uint8_t[req->getSize()]);
MemTestSenderState *state = new MemTestSenderState(result);
pkt->senderState = state;
if (probe) {
cachePort.sendFunctional(pkt);
pkt->makeAtomicResponse();
completeRequest(pkt);
} else {
// req->completionEvent = new MemCompleteEvent(req, result, this);
@@ -420,7 +421,7 @@ MemTest::tick()
<< dec << curTick << endl;
}
*/
Packet *pkt = new Packet(req, Packet::WriteReq, Packet::Broadcast);
PacketPtr pkt = new Packet(req, Packet::WriteReq, Packet::Broadcast);
uint8_t *pkt_data = new uint8_t[req->getSize()];
pkt->dataDynamicArray(pkt_data);
memcpy(pkt_data, &data, req->getSize());
@@ -431,6 +432,7 @@ MemTest::tick()
if (probe) {
cachePort.sendFunctional(pkt);
pkt->makeAtomicResponse();
completeRequest(pkt);
} else {
// req->completionEvent = new MemCompleteEvent(req, NULL, this);
@@ -499,7 +501,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(MemTest)
// SimObjectParam<PhysicalMemory *> check_mem;
Param<unsigned> memory_size;
Param<unsigned> percent_reads;
// Param<unsigned> percent_copies;
Param<unsigned> percent_functional;
Param<unsigned> percent_uncacheable;
Param<unsigned> progress_interval;
Param<unsigned> percent_source_unaligned;
@@ -518,7 +520,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(MemTest)
// INIT_PARAM(check_mem, "check memory"),
INIT_PARAM(memory_size, "memory size"),
INIT_PARAM(percent_reads, "target read percentage"),
// INIT_PARAM(percent_copies, "target copy percentage"),
INIT_PARAM(percent_functional, "percentage of access that are functional"),
INIT_PARAM(percent_uncacheable, "target uncacheable percentage"),
INIT_PARAM(progress_interval, "progress report interval (in accesses)"),
INIT_PARAM(percent_source_unaligned,
@@ -535,7 +537,7 @@ END_INIT_SIM_OBJECT_PARAMS(MemTest)
CREATE_SIM_OBJECT(MemTest)
{
return new MemTest(getInstanceName(), /*cache->getInterface(),*/ /*main_mem,*/
/*check_mem,*/ memory_size, percent_reads, /*percent_copies,*/
/*check_mem,*/ memory_size, percent_reads, percent_functional,
percent_uncacheable, progress_interval,
percent_source_unaligned, percent_dest_unaligned,
trace_addr, max_loads, atomic);

16
src/cpu/memtest/memtest.hh
View File

@@ -55,7 +55,7 @@ class MemTest : public MemObject
// PhysicalMemory *check_mem,
unsigned _memorySize,
unsigned _percentReads,
// unsigned _percentCopies,
unsigned _percentFunctional,
unsigned _percentUncacheable,
unsigned _progressInterval,
unsigned _percentSourceUnaligned,
@@ -102,11 +102,11 @@ class MemTest : public MemObject
protected:
virtual bool recvTiming(Packet *pkt);
virtual bool recvTiming(PacketPtr pkt);
virtual Tick recvAtomic(Packet *pkt);
virtual Tick recvAtomic(PacketPtr pkt);
virtual void recvFunctional(Packet *pkt);
virtual void recvFunctional(PacketPtr pkt);
virtual void recvStatusChange(Status status);
@@ -133,7 +133,7 @@ class MemTest : public MemObject
};
// Request *dataReq;
Packet *retryPkt;
PacketPtr retryPkt;
// MemInterface *cacheInterface;
// PhysicalMemory *mainMem;
// PhysicalMemory *checkMem;
@@ -144,7 +144,7 @@ class MemTest : public MemObject
unsigned size; // size of testing memory region
unsigned percentReads; // target percentage of read accesses
// unsigned percentCopies; // target percentage of copy accesses
unsigned percentFunctional; // target percentage of functional accesses
unsigned percentUncacheable;
int id;
@@ -184,9 +184,9 @@ class MemTest : public MemObject
Stats::Scalar<> numCopiesStat;
// called by MemCompleteEvent::process()
void completeRequest(Packet *pkt);
void completeRequest(PacketPtr pkt);
void sendPkt(Packet *pkt);
void sendPkt(PacketPtr pkt);
void doRetry();

2
src/cpu/o3/alpha/dyn_inst.hh
View File

@@ -86,7 +86,7 @@ class AlphaDynInst : public BaseDynInst<Impl>
Fault initiateAcc();
/** Completes the access. Only valid for memory operations. */
Fault completeAcc(Packet *pkt);
Fault completeAcc(PacketPtr pkt);
private:
/** Initializes variables. */

2
src/cpu/o3/alpha/dyn_inst_impl.hh
View File

@@ -100,7 +100,7 @@ AlphaDynInst<Impl>::initiateAcc()
template <class Impl>
Fault
AlphaDynInst<Impl>::completeAcc(Packet *pkt)
AlphaDynInst<Impl>::completeAcc(PacketPtr pkt)
{
this->fault = this->staticInst->completeAcc(pkt, this, this->traceData);

7
src/cpu/o3/cpu.cc
View File

@@ -850,9 +850,6 @@ template <class Impl>
void
FullO3CPU<Impl>::resume()
{
#if FULL_SYSTEM
assert(system->getMemoryMode() == System::Timing);
#endif
fetch.resume();
decode.resume();
rename.resume();
@@ -864,6 +861,10 @@ FullO3CPU<Impl>::resume()
if (_status == SwitchedOut || _status == Idle)
return;
#if FULL_SYSTEM
assert(system->getMemoryMode() == System::Timing);
#endif
if (!tickEvent.scheduled())
tickEvent.schedule(curTick);
_status = Running;

2
src/cpu/o3/fetch.hh
View File

@@ -36,7 +36,7 @@
#include "base/statistics.hh"
#include "base/timebuf.hh"
#include "cpu/pc_event.hh"
#include "mem/packet_impl.hh"
#include "mem/packet.hh"
#include "mem/port.hh"
#include "sim/eventq.hh"

7
src/cpu/o3/fetch_impl.hh
View File

@@ -78,9 +78,12 @@ DefaultFetch<Impl>::IcachePort::recvStatusChange(Status status)
template<class Impl>
bool
DefaultFetch<Impl>::IcachePort::recvTiming(Packet *pkt)
DefaultFetch<Impl>::IcachePort::recvTiming(PacketPtr pkt)
{
fetch->processCacheCompletion(pkt);
if (pkt->isResponse()) {
fetch->processCacheCompletion(pkt);
}
//else Snooped a coherence request, just return
return true;
}

9
src/cpu/o3/lsq_impl.hh
View File

@@ -63,7 +63,14 @@ template <class Impl>
bool
LSQ<Impl>::DcachePort::recvTiming(PacketPtr pkt)
{
lsq->thread[pkt->req->getThreadNum()].completeDataAccess(pkt);
if (pkt->isResponse()) {
lsq->thread[pkt->req->getThreadNum()].completeDataAccess(pkt);
}
else {
//else it is a coherence request, maybe you need to do something
warn("Recieved a coherence request (Invalidate?), 03CPU doesn't"
"update LSQ for these\n");
}
return true;
}

4
src/cpu/o3/lsq_unit.hh
View File

@@ -40,7 +40,7 @@
#include "config/full_system.hh"
#include "base/hashmap.hh"
#include "cpu/inst_seq.hh"
#include "mem/packet_impl.hh"
#include "mem/packet.hh"
#include "mem/port.hh"
/**
@@ -219,7 +219,7 @@ class LSQUnit {
void writeback(DynInstPtr &inst, PacketPtr pkt);
/** Handles completing the send of a store to memory. */
void storePostSend(Packet *pkt);
void storePostSend(PacketPtr pkt);
/** Completes the store at the specified index. */
void completeStore(int store_idx);

2
src/cpu/o3/lsq_unit_impl.hh
View File

@@ -763,7 +763,7 @@ LSQUnit<Impl>::squash(const InstSeqNum &squashed_num)
template <class Impl>
void
LSQUnit<Impl>::storePostSend(Packet *pkt)
LSQUnit<Impl>::storePostSend(PacketPtr pkt)
{
if (isStalled() &&
storeQueue[storeWBIdx].inst->seqNum == stallingStoreIsn) {

2
src/cpu/o3/mips/dyn_inst.hh
View File

@@ -87,7 +87,7 @@ class MipsDynInst : public BaseDynInst<Impl>
Fault initiateAcc();
/** Completes the access. Only valid for memory operations. */
Fault completeAcc(Packet *pkt);
Fault completeAcc(PacketPtr pkt);
private:
/** Initializes variables. */

2
src/cpu/o3/mips/dyn_inst_impl.hh
View File

@@ -100,7 +100,7 @@ MipsDynInst<Impl>::initiateAcc()
template <class Impl>
Fault
MipsDynInst<Impl>::completeAcc(Packet *pkt)
MipsDynInst<Impl>::completeAcc(PacketPtr pkt)
{
this->fault = this->staticInst->completeAcc(pkt, this, this->traceData);

2
src/cpu/ozone/dyn_inst.hh
View File

@@ -133,7 +133,7 @@ class OzoneDynInst : public BaseDynInst<Impl>
Fault initiateAcc();
Fault completeAcc(Packet *pkt);
Fault completeAcc(PacketPtr pkt);
// The register accessor methods provide the index of the
// instruction's operand (e.g., 0 or 1), not the architectural

2
src/cpu/ozone/dyn_inst_impl.hh
View File

@@ -108,7 +108,7 @@ OzoneDynInst<Impl>::initiateAcc()
template <class Impl>
Fault
OzoneDynInst<Impl>::completeAcc(Packet *pkt)
OzoneDynInst<Impl>::completeAcc(PacketPtr pkt)
{
this->fault = this->staticInst->completeAcc(pkt, this, this->traceData);

2
src/cpu/ozone/front_end.hh
View File

@@ -129,7 +129,7 @@ class FrontEnd
const bool is_branch = false, const bool branch_taken = false);
DynInstPtr getInst();
void processCacheCompletion(Packet *pkt);
void processCacheCompletion(PacketPtr pkt);
void addFreeRegs(int num_freed);

2
src/cpu/ozone/front_end_impl.hh
View File

@@ -74,7 +74,7 @@ FrontEnd<Impl>::IcachePort::recvStatusChange(Status status)
template<class Impl>
bool
FrontEnd<Impl>::IcachePort::recvTiming(Packet *pkt)
FrontEnd<Impl>::IcachePort::recvTiming(PacketPtr pkt)
{
fe->processCacheCompletion(pkt);
return true;

2
src/cpu/ozone/lw_lsq.hh
View File

@@ -222,7 +222,7 @@ class OzoneLWLSQ {
void writeback(DynInstPtr &inst, PacketPtr pkt);
/** Handles completing the send of a store to memory. */
void storePostSend(Packet *pkt, DynInstPtr &inst);
void storePostSend(PacketPtr pkt, DynInstPtr &inst);
/** Completes the store at the specified index. */
void completeStore(DynInstPtr &inst);

2
src/cpu/ozone/lw_lsq_impl.hh
View File

@@ -832,7 +832,7 @@ OzoneLWLSQ<Impl>::dumpInsts()
template <class Impl>
void
OzoneLWLSQ<Impl>::storePostSend(Packet *pkt, DynInstPtr &inst)
OzoneLWLSQ<Impl>::storePostSend(PacketPtr pkt, DynInstPtr &inst)
{
if (isStalled() &&
inst->seqNum == stallingStoreIsn) {

15
src/cpu/simple/atomic.cc
View File

@@ -32,7 +32,8 @@
#include "arch/utility.hh"
#include "cpu/exetrace.hh"
#include "cpu/simple/atomic.hh"
#include "mem/packet_impl.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "sim/builder.hh"
#include "sim/system.hh"
@@ -92,21 +93,21 @@ AtomicSimpleCPU::init()
}
bool
AtomicSimpleCPU::CpuPort::recvTiming(Packet *pkt)
AtomicSimpleCPU::CpuPort::recvTiming(PacketPtr pkt)
{
panic("AtomicSimpleCPU doesn't expect recvTiming callback!");
return true;
}
Tick
AtomicSimpleCPU::CpuPort::recvAtomic(Packet *pkt)
AtomicSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt)
{
panic("AtomicSimpleCPU doesn't expect recvAtomic callback!");
//Snooping a coherence request, just return
return curTick;
}
void
AtomicSimpleCPU::CpuPort::recvFunctional(Packet *pkt)
AtomicSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt)
{
//No internal storage to update, just return
return;
@@ -259,7 +260,7 @@ AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
{
// use the CPU's statically allocated read request and packet objects
Request *req = data_read_req;
Packet *pkt = data_read_pkt;
PacketPtr pkt = data_read_pkt;
req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
@@ -341,7 +342,7 @@ AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
{
// use the CPU's statically allocated write request and packet objects
Request *req = data_write_req;
Packet *pkt = data_write_pkt;
PacketPtr pkt = data_write_pkt;
req->setVirt(0, addr, sizeof(T), flags, thread->readPC());

18
src/cpu/simple/atomic.hh
View File

@@ -92,11 +92,11 @@ class AtomicSimpleCPU : public BaseSimpleCPU
protected:
virtual bool recvTiming(Packet *pkt);
virtual bool recvTiming(PacketPtr pkt);
virtual Tick recvAtomic(Packet *pkt);
virtual Tick recvAtomic(PacketPtr pkt);
virtual void recvFunctional(Packet *pkt);
virtual void recvFunctional(PacketPtr pkt);
virtual void recvStatusChange(Status status);
@@ -110,12 +110,12 @@ class AtomicSimpleCPU : public BaseSimpleCPU
CpuPort icachePort;
CpuPort dcachePort;
Request *ifetch_req;
Packet *ifetch_pkt;
Request *data_read_req;
Packet *data_read_pkt;
Request *data_write_req;
Packet *data_write_pkt;
Request *ifetch_req;
PacketPtr ifetch_pkt;
Request *data_read_req;
PacketPtr data_read_pkt;
Request *data_write_req;
PacketPtr data_write_pkt;
bool dcache_access;
Tick dcache_latency;

2
src/cpu/simple/base.cc
View File

@@ -47,7 +47,7 @@
#include "cpu/static_inst.hh"
#include "cpu/thread_context.hh"
#include "kern/kernel_stats.hh"
#include "mem/packet_impl.hh"
#include "mem/packet.hh"
#include "sim/builder.hh"
#include "sim/byteswap.hh"
#include "sim/debug.hh"

71
src/cpu/simple/timing.cc
View File

@@ -32,7 +32,8 @@
#include "arch/utility.hh"
#include "cpu/exetrace.hh"
#include "cpu/simple/timing.hh"
#include "mem/packet_impl.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "sim/builder.hh"
#include "sim/system.hh"
@@ -65,14 +66,14 @@ TimingSimpleCPU::init()
}
Tick
TimingSimpleCPU::CpuPort::recvAtomic(Packet *pkt)
TimingSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt)
{
panic("TimingSimpleCPU doesn't expect recvAtomic callback!");
return curTick;
}
void
TimingSimpleCPU::CpuPort::recvFunctional(Packet *pkt)
TimingSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt)
{
//No internal storage to update, jusst return
return;
@@ -89,7 +90,7 @@ TimingSimpleCPU::CpuPort::recvStatusChange(Status status)
void
TimingSimpleCPU::CpuPort::TickEvent::schedule(Packet *_pkt, Tick t)
TimingSimpleCPU::CpuPort::TickEvent::schedule(PacketPtr _pkt, Tick t)
{
pkt = _pkt;
Event::schedule(t);
@@ -268,7 +269,7 @@ TimingSimpleCPU::read(Addr addr, T &data, unsigned flags)
// Now do the access.
if (fault == NoFault) {
Packet *pkt =
PacketPtr pkt =
new Packet(req, Packet::ReadReq, Packet::Broadcast);
pkt->dataDynamic<T>(new T);
@@ -470,7 +471,7 @@ TimingSimpleCPU::advanceInst(Fault fault)
void
TimingSimpleCPU::completeIfetch(Packet *pkt)
TimingSimpleCPU::completeIfetch(PacketPtr pkt)
{
// received a response from the icache: execute the received
// instruction
@@ -526,19 +527,25 @@ TimingSimpleCPU::IcachePort::ITickEvent::process()
}
bool
TimingSimpleCPU::IcachePort::recvTiming(Packet *pkt)
TimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt)
{
// delay processing of returned data until next CPU clock edge
Tick time = pkt->req->getTime();
while (time < curTick)
time += lat;
if (pkt->isResponse()) {
// delay processing of returned data until next CPU clock edge
Tick time = pkt->req->getTime();
while (time < curTick)
time += lat;
if (time == curTick)
cpu->completeIfetch(pkt);
else
tickEvent.schedule(pkt, time);
if (time == curTick)
cpu->completeIfetch(pkt);
else
tickEvent.schedule(pkt, time);
return true;
return true;
}
else {
//Snooping a Coherence Request, do nothing
return true;
}
}
void
@@ -548,7 +555,7 @@ TimingSimpleCPU::IcachePort::recvRetry()
// waiting to transmit
assert(cpu->ifetch_pkt != NULL);
assert(cpu->_status == IcacheRetry);
Packet *tmp = cpu->ifetch_pkt;
PacketPtr tmp = cpu->ifetch_pkt;
if (sendTiming(tmp)) {
cpu->_status = IcacheWaitResponse;
cpu->ifetch_pkt = NULL;
@@ -556,7 +563,7 @@ TimingSimpleCPU::IcachePort::recvRetry()
}
void
TimingSimpleCPU::completeDataAccess(Packet *pkt)
TimingSimpleCPU::completeDataAccess(PacketPtr pkt)
{
// received a response from the dcache: complete the load or store
// instruction
@@ -598,19 +605,25 @@ TimingSimpleCPU::completeDrain()
}
bool
TimingSimpleCPU::DcachePort::recvTiming(Packet *pkt)
TimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt)
{
// delay processing of returned data until next CPU clock edge
Tick time = pkt->req->getTime();
while (time < curTick)
time += lat;
if (pkt->isResponse()) {
// delay processing of returned data until next CPU clock edge
Tick time = pkt->req->getTime();
while (time < curTick)
time += lat;
if (time == curTick)
cpu->completeDataAccess(pkt);
else
tickEvent.schedule(pkt, time);
if (time == curTick)
cpu->completeDataAccess(pkt);
else
tickEvent.schedule(pkt, time);
return true;
return true;
}
else {
//Snooping a coherence req, do nothing
return true;
}
}
void
@@ -626,7 +639,7 @@ TimingSimpleCPU::DcachePort::recvRetry()
// waiting to transmit
assert(cpu->dcache_pkt != NULL);
assert(cpu->_status == DcacheRetry);
Packet *tmp = cpu->dcache_pkt;
PacketPtr tmp = cpu->dcache_pkt;
if (sendTiming(tmp)) {
cpu->_status = DcacheWaitResponse;
// memory system takes ownership of packet

20
src/cpu/simple/timing.hh
View File

@@ -84,9 +84,9 @@ class TimingSimpleCPU : public BaseSimpleCPU
protected:
virtual Tick recvAtomic(Packet *pkt);
virtual Tick recvAtomic(PacketPtr pkt);
virtual void recvFunctional(Packet *pkt);
virtual void recvFunctional(PacketPtr pkt);
virtual void recvStatusChange(Status status);
@@ -96,13 +96,13 @@ class TimingSimpleCPU : public BaseSimpleCPU
struct TickEvent : public Event
{
Packet *pkt;
PacketPtr pkt;
TimingSimpleCPU *cpu;
TickEvent(TimingSimpleCPU *_cpu)
:Event(&mainEventQueue), cpu(_cpu) {}
const char *description() { return "Timing CPU clock event"; }
void schedule(Packet *_pkt, Tick t);
void schedule(PacketPtr _pkt, Tick t);
};
};
@@ -117,7 +117,7 @@ class TimingSimpleCPU : public BaseSimpleCPU
protected:
virtual bool recvTiming(Packet *pkt);
virtual bool recvTiming(PacketPtr pkt);
virtual void recvRetry();
@@ -144,7 +144,7 @@ class TimingSimpleCPU : public BaseSimpleCPU
protected:
virtual bool recvTiming(Packet *pkt);
virtual bool recvTiming(PacketPtr pkt);
virtual void recvRetry();
@@ -163,8 +163,8 @@ class TimingSimpleCPU : public BaseSimpleCPU
IcachePort icachePort;
DcachePort dcachePort;
Packet *ifetch_pkt;
Packet *dcache_pkt;
PacketPtr ifetch_pkt;
PacketPtr dcache_pkt;
int cpu_id;
Tick previousTick;
@@ -192,8 +192,8 @@ class TimingSimpleCPU : public BaseSimpleCPU
Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
void fetch();
void completeIfetch(Packet *);
void completeDataAccess(Packet *);
void completeIfetch(PacketPtr );
void completeDataAccess(PacketPtr );
void advanceInst(Fault fault);
private:
void completeDrain();