diff --git a/src/arch/alpha/tlb.hh b/src/arch/alpha/tlb.hh
index ed7e7ab614..b6261769f3 100644
--- a/src/arch/alpha/tlb.hh
+++ b/src/arch/alpha/tlb.hh
@@ -42,7 +42,7 @@
 #include "base/statistics.hh"
 #include "mem/request.hh"
 #include "params/AlphaTLB.hh"
-#include "sim/fault.hh"
+#include "sim/fault_fwd.hh"
 #include "sim/tlb.hh"
 
 class ThreadContext;
diff --git a/src/arch/arm/table_walker.hh b/src/arch/arm/table_walker.hh
index 2739973e8e..267a7ad260 100644
--- a/src/arch/arm/table_walker.hh
+++ b/src/arch/arm/table_walker.hh
@@ -49,7 +49,7 @@
 #include "mem/request.hh"
 #include "params/ArmTableWalker.hh"
 #include "sim/eventq.hh"
-#include "sim/fault.hh"
+#include "sim/fault_fwd.hh"
 
 class DmaPort;
 class ThreadContext;
diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh
index 1374123b21..e60de38dde 100644
--- a/src/arch/arm/tlb.hh
+++ b/src/arch/arm/tlb.hh
@@ -52,7 +52,7 @@
 #include "base/statistics.hh"
 #include "mem/request.hh"
 #include "params/ArmTLB.hh"
-#include "sim/fault.hh"
+#include "sim/fault_fwd.hh"
 #include "sim/tlb.hh"
 
 class ThreadContext;
diff --git a/src/arch/mips/isa.hh b/src/arch/mips/isa.hh
index 6adf6bddc8..8032d20d01 100644
--- a/src/arch/mips/isa.hh
+++ b/src/arch/mips/isa.hh
@@ -38,7 +38,7 @@
 #include "arch/mips/registers.hh"
 #include "arch/mips/types.hh"
 #include "sim/eventq.hh"
-#include "sim/fault.hh"
+#include "sim/fault_fwd.hh"
 
 class BaseCPU;
 class Checkpoint;
diff --git a/src/arch/mips/tlb.hh b/src/arch/mips/tlb.hh
index cb2e434cb6..5c8b102636 100644
--- a/src/arch/mips/tlb.hh
+++ b/src/arch/mips/tlb.hh
@@ -44,7 +44,7 @@
 #include "base/statistics.hh"
 #include "mem/request.hh"
 #include "params/MipsTLB.hh"
-#include "sim/fault.hh"
+#include "sim/fault_fwd.hh"
 #include "sim/tlb.hh"
 #include "sim/sim_object.hh"
 
diff --git a/src/arch/power/tlb.hh b/src/arch/power/tlb.hh
index 7e5638cf1b..c4e3fadaab 100644
--- a/src/arch/power/tlb.hh
+++ b/src/arch/power/tlb.hh
@@ -46,7 +46,7 @@
 #include "base/statistics.hh"
 #include "mem/request.hh"
 #include "params/PowerTLB.hh"
-#include "sim/fault.hh"
+#include "sim/fault_fwd.hh"
 #include "sim/tlb.hh"
 
 class ThreadContext;
diff --git a/src/arch/sparc/tlb.hh b/src/arch/sparc/tlb.hh
index fa9ebada69..76ef23b649 100644
--- a/src/arch/sparc/tlb.hh
+++ b/src/arch/sparc/tlb.hh
@@ -37,7 +37,7 @@
 #include "config/full_system.hh"
 #include "mem/request.hh"
 #include "params/SparcTLB.hh"
-#include "sim/fault.hh"
+#include "sim/fault_fwd.hh"
 #include "sim/tlb.hh"
 
 class ThreadContext;
diff --git a/src/arch/sparc/utility.hh b/src/arch/sparc/utility.hh
index b1c099a97d..d69b42d01d 100644
--- a/src/arch/sparc/utility.hh
+++ b/src/arch/sparc/utility.hh
@@ -38,7 +38,7 @@
 #include "base/bitfield.hh"
 #include "cpu/static_inst.hh"
 #include "cpu/thread_context.hh"
-#include "sim/fault.hh"
+#include "sim/fault_fwd.hh"
 
 namespace SparcISA
 {
diff --git a/src/arch/x86/tlb.hh b/src/arch/x86/tlb.hh
index 025418dc7f..0e96b26b82 100644
--- a/src/arch/x86/tlb.hh
+++ b/src/arch/x86/tlb.hh
@@ -50,7 +50,7 @@
 #include "mem/mem_object.hh"
 #include "mem/request.hh"
 #include "params/X86TLB.hh"
-#include "sim/fault.hh"
+#include "sim/fault_fwd.hh"
 #include "sim/tlb.hh"
 #include "sim/sim_object.hh"
 
diff --git a/src/cpu/static_inst.hh b/src/cpu/static_inst.hh
index 15ac444aee..9334968644 100644
--- a/src/cpu/static_inst.hh
+++ b/src/cpu/static_inst.hh
@@ -43,7 +43,7 @@
 #include "base/refcnt.hh"
 #include "base/types.hh"
 #include "cpu/op_class.hh"
-#include "sim/fault.hh"
+#include "sim/fault_fwd.hh"
 
 // forward declarations
 struct AlphaSimpleImpl;
diff --git a/src/sim/fault.hh b/src/sim/fault_fwd.hh
similarity index 100%
rename from src/sim/fault.hh
rename to src/sim/fault_fwd.hh
diff --git a/src/sim/faults.hh b/src/sim/faults.hh
index 27cc7538c5..779e34c8f8 100644
--- a/src/sim/faults.hh
+++ b/src/sim/faults.hh
@@ -34,7 +34,7 @@
 
 #include "base/refcnt.hh"
 #include "base/types.hh"
-#include "sim/fault.hh"
+#include "sim/fault_fwd.hh"
 #include "sim/stats.hh"
 #include "config/full_system.hh"
 #include "cpu/static_inst.hh"
diff --git a/src/sim/tlb.hh b/src/sim/tlb.hh
index a3e5c22c7b..1512bc0fae 100644
--- a/src/sim/tlb.hh
+++ b/src/sim/tlb.hh
@@ -33,7 +33,7 @@
 
 #include "base/misc.hh"
 #include "mem/request.hh"
-#include "sim/fault.hh"
+#include "sim/fault_fwd.hh"
 #include "sim/sim_object.hh"
 
 class ThreadContext;