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stats: Update stats to reflect bus retry changes

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This patch updates the stats after splitting the bus retry into
waiting for the bus and waiting for the peer.
This commit is contained in:
Andreas Hansson
2013-03-26 14:46:49 -04:00
parent 93a8423dea
commit 08f7a8bc00
23 changed files with 13764 additions and 13765 deletions
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800
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
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File diff suppressed because it is too large Load Diff

454
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
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@@ -4,11 +4,11 @@ sim_seconds 1.913475 # Nu
sim_ticks 1913474690000 # Number of ticks simulated
final_tick 1913474690000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1324010 # Simulator instruction rate (inst/s)
host_op_rate 1324010 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 45134311907 # Simulator tick rate (ticks/s)
host_mem_usage 328328 # Number of bytes of host memory used
host_seconds 42.40 # Real time elapsed on the host
host_inst_rate 960952 # Simulator instruction rate (inst/s)
host_op_rate 960952 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 32757999490 # Simulator tick rate (ticks/s)
host_mem_usage 329472 # Number of bytes of host memory used
host_seconds 58.41 # Real time elapsed on the host
sim_insts 56131527 # Number of instructions simulated
sim_ops 56131527 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 850560 # Number of bytes read from this memory
@@ -40,7 +40,7 @@ system.physmem.bw_total::tsunami.ide 1386010 # To
system.physmem.bw_total::total 18692227 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 443158 # Total number of read requests seen
system.physmem.writeReqs 115703 # Total number of write requests seen
system.physmem.cpureqs 560726 # Reqs generatd by CPU via cache - shady
system.physmem.cpureqs 559001 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 28362112 # Total number of bytes read from memory
system.physmem.bytesWritten 7404992 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 28362112 # bytesRead derated as per pkt->getSize()
@@ -80,7 +80,7 @@ system.physmem.perBankWrReqs::13 7186 # Tr
system.physmem.perBankWrReqs::14 7115 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 7077 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 1735 # Number of times wr buffer was full causing retry
system.physmem.numWrRetry 10 # Number of times wr buffer was full causing retry
system.physmem.totGap 1913462790000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
@@ -96,26 +96,26 @@ system.physmem.writePktSize::3 0 # Ca
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
system.physmem.writePktSize::6 115703 # Categorize write packet sizes
system.physmem.rdQLenPdf::0 402452 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 4725 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 3681 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 2218 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 3124 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 2960 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 2702 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::0 402453 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 4723 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 3684 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 2217 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 3126 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 2958 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 2701 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 2703 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 2646 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 2585 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 1528 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 1461 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 1423 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 1368 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 1422 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 1367 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 1353 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 1388 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 1604 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 1473 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 916 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 777 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 1390 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 1608 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 1477 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 912 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 773 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 10 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
@@ -132,11 +132,11 @@ system.physmem.wrQLenPdf::0 3531 # Wh
system.physmem.wrQLenPdf::1 3690 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 4106 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 4152 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 4652 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 5003 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 5013 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 5015 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 5016 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 4653 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 5005 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 5014 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 5016 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 5017 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 5031 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 5031 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 5031 # What write queue length does an incoming req see
@@ -155,19 +155,19 @@ system.physmem.wrQLenPdf::23 1500 # Wh
system.physmem.wrQLenPdf::24 1341 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 925 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 879 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 379 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 28 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 18 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 16 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 15 # What write queue length does an incoming req see
system.physmem.totQLat 4718928250 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 13231418250 # Sum of mem lat for all requests
system.physmem.wrQLenPdf::27 378 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 26 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 17 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 15 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 14 # What write queue length does an incoming req see
system.physmem.totQLat 4710239250 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 13222743000 # Sum of mem lat for all requests
system.physmem.totBusLat 2215485000 # Total cycles spent in databus access
system.physmem.totBankLat 6297005000 # Total cycles spent in bank access
system.physmem.avgQLat 10649.88 # Average queueing delay per request
system.physmem.avgBankLat 14211.35 # Average bank access latency per request
system.physmem.totBankLat 6297018750 # Total cycles spent in bank access
system.physmem.avgQLat 10630.27 # Average queueing delay per request
system.physmem.avgBankLat 14211.38 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
system.physmem.avgMemAccLat 29861.22 # Average memory access latency
system.physmem.avgMemAccLat 29841.64 # Average memory access latency
system.physmem.avgRdBW 14.82 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 3.87 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 14.82 # Average consumed read bandwidth in MB/s
@@ -200,12 +200,12 @@ system.iocache.overall_misses::tsunami.ide 41725 #
system.iocache.overall_misses::total 41725 # number of overall misses
system.iocache.ReadReq_miss_latency::tsunami.ide 20927998 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 20927998 # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::tsunami.ide 10661973806 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total 10661973806 # number of WriteReq miss cycles
system.iocache.demand_miss_latency::tsunami.ide 10682901804 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 10682901804 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::tsunami.ide 10682901804 # number of overall miss cycles
system.iocache.overall_miss_latency::total 10682901804 # number of overall miss cycles
system.iocache.WriteReq_miss_latency::tsunami.ide 10653271428 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total 10653271428 # number of WriteReq miss cycles
system.iocache.demand_miss_latency::tsunami.ide 10674199426 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 10674199426 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::tsunami.ide 10674199426 # number of overall miss cycles
system.iocache.overall_miss_latency::total 10674199426 # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses)
@@ -224,17 +224,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120971.086705 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 120971.086705 # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::tsunami.ide 256593.516702 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 256593.516702 # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::tsunami.ide 256031.199617 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 256031.199617 # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 256031.199617 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 256031.199617 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 285723 # number of cycles access was blocked
system.iocache.WriteReq_avg_miss_latency::tsunami.ide 256384.083269 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 256384.083269 # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::tsunami.ide 255822.634536 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 255822.634536 # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 255822.634536 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 255822.634536 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 285520 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 27146 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 27149 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs 10.525418 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_mshrs 10.516778 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
@@ -250,12 +250,12 @@ system.iocache.overall_mshr_misses::tsunami.ide 41725
system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11931249 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 11931249 # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8499962078 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total 8499962078 # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide 8511893327 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 8511893327 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide 8511893327 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 8511893327 # number of overall MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8491261949 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total 8491261949 # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide 8503193198 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 8503193198 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide 8503193198 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 8503193198 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses
@@ -266,12 +266,12 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 1
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68966.757225 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 68966.757225 # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 204562.044619 # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 204562.044619 # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 203999.840072 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 203999.840072 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 203999.840072 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 203999.840072 # average overall mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 204352.665311 # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 204352.665311 # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 203791.328892 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 203791.328892 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 203791.328892 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 203791.328892 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
@@ -335,8 +335,8 @@ system.cpu.num_fp_register_writes 166418 # nu
system.cpu.num_mem_refs 15461819 # number of memory refs
system.cpu.num_load_insts 9093811 # Number of load instructions
system.cpu.num_store_insts 6368008 # Number of store instructions
system.cpu.num_idle_cycles 3593003741.998122 # Number of idle cycles
system.cpu.num_busy_cycles 233945638.001878 # Number of busy cycles
system.cpu.num_idle_cycles 3593002703.998122 # Number of idle cycles
system.cpu.num_busy_cycles 233946676.001878 # Number of busy cycles
system.cpu.not_idle_fraction 0.061131 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.938869 # Percentage of idle cycles
system.cpu.kern.inst.arm 0 # number of arm instructions executed
@@ -352,10 +352,10 @@ system.cpu.kern.ipl_good::21 131 0.09% 49.40% # nu
system.cpu.kern.ipl_good::22 1933 1.30% 50.69% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::31 73532 49.31% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::total 149128 # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_ticks::0 1858610780000 97.13% 97.13% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::0 1858610730000 97.13% 97.13% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::21 91300500 0.00% 97.14% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::22 737276500 0.04% 97.18% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::31 54034599000 2.82% 100.00% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::31 54034649000 2.82% 100.00% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::total 1913473956000 # number of cycles we spent at this ipl
system.cpu.kern.ipl_used::0 0.981749 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
@@ -420,9 +420,9 @@ system.cpu.kern.mode_switch_good::kernel 0.323898 # fr
system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::idle 0.080553 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::total 0.392402 # fraction of useful protection mode switches
system.cpu.kern.mode_ticks::kernel 45394142000 2.37% 2.37% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::user 5131394000 0.27% 2.64% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::idle 1862948418000 97.36% 100.00% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::kernel 45394332000 2.37% 2.37% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::user 5131699000 0.27% 2.64% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::idle 1862947923000 97.36% 100.00% # number of ticks spent at the given mode
system.cpu.kern.swap_context 4175 # number of times the context was actually changed
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
@@ -476,12 +476,12 @@ system.cpu.icache.demand_misses::cpu.inst 928628 # n
system.cpu.icache.demand_misses::total 928628 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 928628 # number of overall misses
system.cpu.icache.overall_misses::total 928628 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 12770278000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 12770278000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 12770278000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 12770278000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 12770278000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 12770278000 # number of overall miss cycles
system.cpu.icache.ReadReq_miss_latency::cpu.inst 12770432000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 12770432000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 12770432000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 12770432000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 12770432000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 12770432000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 56143366 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 56143366 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 56143366 # number of demand (read+write) accesses
@@ -494,12 +494,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.016540
system.cpu.icache.demand_miss_rate::total 0.016540 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.016540 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.016540 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13751.769277 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13751.769277 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13751.769277 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13751.769277 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13751.769277 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13751.769277 # average overall miss latency
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13751.935113 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13751.935113 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13751.935113 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13751.935113 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13751.935113 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13751.935113 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35600.705826 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35600.705826 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50144.547028 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 32201.696779 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 32794.721257 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50144.547028 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 32201.696779 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 32794.721257 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
@@ -703,47 +703,47 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 1389801 # number of replacements
system.cpu.dcache.replacements 1389808 # number of replacements
system.cpu.dcache.tagsinuse 511.980871 # Cycle average of tags in use
system.cpu.dcache.total_refs 14037928 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 1390313 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 10.096955 # Average number of references to valid blocks.
system.cpu.dcache.total_refs 14037921 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 1390320 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 10.096899 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 93552000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 511.980871 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999963 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999963 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 7807394 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 7807394 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::cpu.data 7807387 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 7807387 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 5848285 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 5848285 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 183004 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 183004 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 199228 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 199228 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 13655679 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 13655679 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 13655679 # number of overall hits
system.cpu.dcache.overall_hits::total 13655679 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1068700 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1068700 # number of ReadReq misses
system.cpu.dcache.demand_hits::cpu.data 13655672 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 13655672 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 13655672 # number of overall hits
system.cpu.dcache.overall_hits::total 13655672 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1068707 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1068707 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 304387 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 304387 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 17244 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 17244 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data 1373087 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 1373087 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 1373087 # number of overall misses
system.cpu.dcache.overall_misses::total 1373087 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 22867911000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 22867911000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 8385686000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 8385686000 # number of WriteReq miss cycles
system.cpu.dcache.demand_misses::cpu.data 1373094 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 1373094 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 1373094 # number of overall misses
system.cpu.dcache.overall_misses::total 1373094 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 22868320000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 22868320000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 8385649000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 8385649000 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 228869000 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 228869000 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 31253597000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 31253597000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 31253597000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 31253597000 # number of overall miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 31253969000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 31253969000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 31253969000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 31253969000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 8876094 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 8876094 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 6152672 # number of WriteReq accesses(hits+misses)
@@ -756,8 +756,8 @@ system.cpu.dcache.demand_accesses::cpu.data 15028766 #
system.cpu.dcache.demand_accesses::total 15028766 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 15028766 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 15028766 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120402 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.120402 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120403 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.120403 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049472 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.049472 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086113 # miss rate for LoadLockedReq accesses
@@ -766,16 +766,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.091364
system.cpu.dcache.demand_miss_rate::total 0.091364 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.091364 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.091364 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21397.876860 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 21397.876860 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27549.422282 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 27549.422282 # average WriteReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21398.119410 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 21398.119410 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27549.300726 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 27549.300726 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13272.384598 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13272.384598 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 22761.556260 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 22761.556260 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 22761.556260 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 22761.556260 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 22761.711143 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 22761.711143 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 22761.711143 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 22761.711143 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -784,36 +784,36 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 834498 # number of writebacks
system.cpu.dcache.writebacks::total 834498 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1068700 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 1068700 # number of ReadReq MSHR misses
system.cpu.dcache.writebacks::writebacks 834499 # number of writebacks
system.cpu.dcache.writebacks::total 834499 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1068707 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 1068707 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304387 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 304387 # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17244 # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total 17244 # number of LoadLockedReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 1373087 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 1373087 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 1373087 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 1373087 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 20730511000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 20730511000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7776912000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 7776912000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_misses::cpu.data 1373094 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 1373094 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 1373094 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 1373094 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 20730906000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 20730906000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7776875000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 7776875000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 194381000 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 194381000 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28507423000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 28507423000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28507423000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 28507423000 # number of overall MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28507781000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 28507781000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28507781000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 28507781000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424236000 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424236000 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2011665000 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2011665000 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3435901000 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 3435901000 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120402 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120402 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120403 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120403 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049472 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049472 # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086113 # mshr miss rate for LoadLockedReq accesses
@@ -822,16 +822,16 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091364
system.cpu.dcache.demand_mshr_miss_rate::total 0.091364 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091364 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.091364 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19397.876860 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19397.876860 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25549.422282 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25549.422282 # average WriteReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19398.119410 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19398.119410 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25549.300726 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25549.300726 # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11272.384598 # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11272.384598 # average LoadLockedReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20761.556260 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 20761.556260 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20761.556260 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 20761.556260 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20761.711143 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 20761.711143 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20761.711143 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 20761.711143 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency

716
tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
View File

@@ -4,13 +4,13 @@ sim_seconds 5.195162 # Nu
sim_ticks 5195162021000 # Number of ticks simulated
final_tick 5195162021000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 926995 # Simulator instruction rate (inst/s)
host_op_rate 1786992 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 37543942770 # Simulator tick rate (ticks/s)
host_mem_usage 611560 # Number of bytes of host memory used
host_seconds 138.38 # Real time elapsed on the host
sim_insts 128273323 # Number of instructions simulated
sim_ops 247275942 # Number of ops (including micro ops) simulated
host_inst_rate 697576 # Simulator instruction rate (inst/s)
host_op_rate 1344736 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 28252317760 # Simulator tick rate (ticks/s)
host_mem_usage 611664 # Number of bytes of host memory used
host_seconds 183.88 # Real time elapsed on the host
sim_insts 128273373 # Number of instructions simulated
sim_ops 247275988 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::pc.south_bridge.ide 2861312 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory
@@ -48,16 +48,16 @@ system.physmem.bw_total::cpu.data 1734722 # To
system.physmem.bw_total::total 4007716 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 198400 # Total number of read requests seen
system.physmem.writeReqs 126924 # Total number of write requests seen
system.physmem.cpureqs 327581 # Reqs generatd by CPU via cache - shady
system.physmem.cpureqs 326952 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 12697600 # Total number of bytes read from memory
system.physmem.bytesWritten 8123136 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 12697600 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 8123136 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 58 # Number of read reqs serviced by write Q
system.physmem.servicedByWrQ 57 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 1624 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 12569 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 12080 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 12233 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 12234 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 12524 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 12268 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 12127 # Track reads on a per bank basis
@@ -88,7 +88,7 @@ system.physmem.perBankWrReqs::13 7628 # Tr
system.physmem.perBankWrReqs::14 7886 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 8059 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 633 # Number of times wr buffer was full causing retry
system.physmem.numWrRetry 4 # Number of times wr buffer was full causing retry
system.physmem.totGap 5195161957500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
@@ -104,27 +104,27 @@ system.physmem.writePktSize::3 0 # Ca
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
system.physmem.writePktSize::6 126924 # Categorize write packet sizes
system.physmem.rdQLenPdf::0 155117 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 8774 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 6658 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 3415 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 3396 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 2811 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 2249 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 2165 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 2071 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 2021 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 1317 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 1212 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 1130 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 1042 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 954 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 971 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 1103 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 1084 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 505 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 310 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 37 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::0 155109 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 8773 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 6640 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 3418 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 3389 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 2825 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 2250 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 2164 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 2085 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 2006 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 1319 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 1198 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 1104 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 1044 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 968 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 978 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 1114 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 1077 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 526 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 320 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 36 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
@@ -136,15 +136,15 @@ system.physmem.rdQLenPdf::28 0 # Wh
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 4189 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 4520 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 5322 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 5434 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 5475 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 5503 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 5510 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 5511 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 5512 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::0 4196 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 4527 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 5315 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 5432 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 5480 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 5508 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 5513 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 5513 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 5514 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 5519 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 5518 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 5518 # What write queue length does an incoming req see
@@ -159,23 +159,23 @@ system.physmem.wrQLenPdf::19 5518 # Wh
system.physmem.wrQLenPdf::20 5518 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 5518 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 5518 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 1330 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 999 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 197 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 85 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 16 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 9 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 8 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 7 # What write queue length does an incoming req see
system.physmem.totQLat 4073325250 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 7869155250 # Sum of mem lat for all requests
system.physmem.totBusLat 991710000 # Total cycles spent in databus access
system.physmem.totBankLat 2804120000 # Total cycles spent in bank access
system.physmem.avgQLat 20536.88 # Average queueing delay per request
system.physmem.avgBankLat 14137.80 # Average bank access latency per request
system.physmem.wrQLenPdf::23 1323 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 992 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 204 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 87 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 39 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 11 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 6 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 6 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 5 # What write queue length does an incoming req see
system.physmem.totQLat 4118897499 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 7915241249 # Sum of mem lat for all requests
system.physmem.totBusLat 991715000 # Total cycles spent in databus access
system.physmem.totBankLat 2804628750 # Total cycles spent in bank access
system.physmem.avgQLat 20766.54 # Average queueing delay per request
system.physmem.avgBankLat 14140.30 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
system.physmem.avgMemAccLat 39674.68 # Average memory access latency
system.physmem.avgMemAccLat 39906.83 # Average memory access latency
system.physmem.avgRdBW 2.44 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 1.56 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 2.44 # Average consumed read bandwidth in MB/s
@@ -184,8 +184,8 @@ system.physmem.peakBW 12800.00 # Th
system.physmem.busUtil 0.03 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.00 # Average read queue length over time
system.physmem.avgWrQLen 12.66 # Average write queue length over time
system.physmem.readRowHits 175586 # Number of row buffer hits during reads
system.physmem.writeRowHits 94818 # Number of row buffer hits during writes
system.physmem.readRowHits 175593 # Number of row buffer hits during reads
system.physmem.writeRowHits 94810 # Number of row buffer hits during writes
system.physmem.readRowHitRate 88.53 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 74.70 # Row buffer hit rate for writes
system.physmem.avgGap 15969193.66 # Average gap between requests
@@ -206,14 +206,14 @@ system.iocache.demand_misses::pc.south_bridge.ide 47564
system.iocache.demand_misses::total 47564 # number of demand (read+write) misses
system.iocache.overall_misses::pc.south_bridge.ide 47564 # number of overall misses
system.iocache.overall_misses::total 47564 # number of overall misses
system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 139479932 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 139479932 # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10699969160 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total 10699969160 # number of WriteReq miss cycles
system.iocache.demand_miss_latency::pc.south_bridge.ide 10839449092 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 10839449092 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::pc.south_bridge.ide 10839449092 # number of overall miss cycles
system.iocache.overall_miss_latency::total 10839449092 # number of overall miss cycles
system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 137986397 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 137986397 # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10732357682 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total 10732357682 # number of WriteReq miss cycles
system.iocache.demand_miss_latency::pc.south_bridge.ide 10870344079 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 10870344079 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::pc.south_bridge.ide 10870344079 # number of overall miss cycles
system.iocache.overall_miss_latency::total 10870344079 # number of overall miss cycles
system.iocache.ReadReq_accesses::pc.south_bridge.ide 844 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 844 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses)
@@ -230,19 +230,19 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 165260.582938 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 165260.582938 # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 229023.312500 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 229023.312500 # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 227891.873938 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 227891.873938 # average overall miss latency
system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 227891.873938 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 227891.873938 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 173195 # number of cycles access was blocked
system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 163490.991706 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 163490.991706 # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 229716.559974 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 229716.559974 # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 228541.419540 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 228541.419540 # average overall miss latency
system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 228541.419540 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 228541.419540 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 175903 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 16181 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 16290 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs 10.703603 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_mshrs 10.798220 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
@@ -256,14 +256,14 @@ system.iocache.demand_mshr_misses::pc.south_bridge.ide 47564
system.iocache.demand_mshr_misses::total 47564 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::pc.south_bridge.ide 47564 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 47564 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 95570962 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 95570962 # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 8269165315 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total 8269165315 # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8364736277 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 8364736277 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8364736277 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 8364736277 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 94077427 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 94077427 # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 8301559588 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total 8301559588 # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8395637015 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 8395637015 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8395637015 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 8395637015 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses
@@ -272,14 +272,14 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 113235.736967 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 113235.736967 # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 176994.120612 # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 176994.120612 # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 175862.759167 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 175862.759167 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 175862.759167 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 175862.759167 # average overall mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 111466.145735 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 111466.145735 # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 177687.491182 # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 177687.491182 # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 176512.425679 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 176512.425679 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 176512.425679 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 176512.425679 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
@@ -296,72 +296,72 @@ system.pc.south_bridge.ide.disks1.dma_write_txs 1
system.cpu.numCycles 10390324042 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 128273323 # Number of instructions committed
system.cpu.committedOps 247275942 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 232011652 # Number of integer alu accesses
system.cpu.committedInsts 128273373 # Number of instructions committed
system.cpu.committedOps 247275988 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 232011695 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 0 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 23157367 # number of instructions that are conditional controls
system.cpu.num_int_insts 232011652 # number of integer instructions
system.cpu.num_conditional_control_insts 23157364 # number of instructions that are conditional controls
system.cpu.num_int_insts 232011695 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions
system.cpu.num_int_register_reads 567056066 # number of times the integer registers were read
system.cpu.num_int_register_writes 293242220 # number of times the integer registers were written
system.cpu.num_int_register_reads 567056109 # number of times the integer registers were read
system.cpu.num_int_register_writes 293242196 # number of times the integer registers were written
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_mem_refs 22232130 # number of memory refs
system.cpu.num_load_insts 13871776 # Number of load instructions
system.cpu.num_store_insts 8360354 # Number of store instructions
system.cpu.num_idle_cycles 9789674914.998116 # Number of idle cycles
system.cpu.num_busy_cycles 600649127.001884 # Number of busy cycles
system.cpu.not_idle_fraction 0.057809 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.942191 # Percentage of idle cycles
system.cpu.num_mem_refs 22232145 # number of memory refs
system.cpu.num_load_insts 13871789 # Number of load instructions
system.cpu.num_store_insts 8360356 # Number of store instructions
system.cpu.num_idle_cycles 9789660715.998116 # Number of idle cycles
system.cpu.num_busy_cycles 600663326.001884 # Number of busy cycles
system.cpu.not_idle_fraction 0.057810 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.942190 # Percentage of idle cycles
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
system.cpu.icache.replacements 791510 # number of replacements
system.cpu.icache.replacements 791527 # number of replacements
system.cpu.icache.tagsinuse 510.376104 # Cycle average of tags in use
system.cpu.icache.total_refs 144497671 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 792022 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 182.441486 # Average number of references to valid blocks.
system.cpu.icache.total_refs 144497724 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 792039 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 182.437638 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 159800886000 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 510.376104 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.996828 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.996828 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 144497671 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 144497671 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 144497671 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 144497671 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 144497671 # number of overall hits
system.cpu.icache.overall_hits::total 144497671 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 792029 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 792029 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 792029 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 792029 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 792029 # number of overall misses
system.cpu.icache.overall_misses::total 792029 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 10955241500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 10955241500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 10955241500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 10955241500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 10955241500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 10955241500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 145289700 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 145289700 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 145289700 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 145289700 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 145289700 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 145289700 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_hits::cpu.inst 144497724 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 144497724 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 144497724 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 144497724 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 144497724 # number of overall hits
system.cpu.icache.overall_hits::total 144497724 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 792046 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 792046 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 792046 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 792046 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 792046 # number of overall misses
system.cpu.icache.overall_misses::total 792046 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 10958971500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 10958971500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 10958971500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 10958971500 # number of demand (read+write) miss cycles
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system.cpu.icache.overall_miss_latency::total 10958971500 # number of overall miss cycles
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system.cpu.icache.demand_avg_miss_latency::cpu.inst 13831.869161 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13831.869161 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13831.869161 # average overall miss latency
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system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13836.281605 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13836.281605 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13836.281605 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13836.281605 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13836.281605 # average overall miss latency
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system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -370,40 +370,40 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu.icache.overall_mshr_miss_latency::total 9374879500 # number of overall MSHR miss cycles
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system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11831.869161 # average overall mshr miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11836.281605 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11836.281605 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 11836.281605 # average overall mshr miss latency
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system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 7860.975041 # average overall mshr miss latency
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@@ -672,17 +672,17 @@ system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
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system.cpu.l2cache.avg_refs 22.981837 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016252 # miss rate for ReadReq accesses
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system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1295316957 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1923433320 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 14542846 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 14542846 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4190411275 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4190411275 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 631288357 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1297548953 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1929174816 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 14616845 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 14616845 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4191303025 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4191303025 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 56251 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 281255 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 627778857 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5485728232 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 6113844595 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 631288357 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5488851978 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 6120477841 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 56251 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 281255 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 627778857 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5485728232 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 6113844595 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 631288357 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5488851978 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 6120477841 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86591175500 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86591175500 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2305021500 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2305021500 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 88896197000 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 88896197000 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2305022500 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2305022500 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 88896198000 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 88896198000 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000158 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001812 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016252 # mshr miss rate for ReadReq accesses
@@ -867,37 +867,37 @@ system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021737
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019584 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.823174 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.823174 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.362485 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.362485 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.362488 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.362488 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000158 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001812 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016252 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087573 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.063901 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087572 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.063900 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000158 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001812 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016252 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087573 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.063901 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087572 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.063900 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 56251 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 56251 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 48770.886964 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45633.854395 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 46613.996074 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10661.910557 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10661.910557 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36966.171554 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36966.171554 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 49043.533017 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45712.487335 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 46753.140004 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10716.162023 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10716.162023 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36974.038224 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36974.038224 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 56251 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 56251 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 48770.886964 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38701.934007 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39540.842415 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49043.533017 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38723.972104 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39583.742448 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 56251 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 56251 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 48770.886964 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38701.934007 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39540.842415 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49043.533017 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38723.972104 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39583.742448 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency

2847
tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt
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File diff suppressed because it is too large Load Diff

24
tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-mem/stats.txt
View File

@@ -4,9 +4,9 @@ sim_seconds 0.100000 # Nu
sim_ticks 100000000000 # Number of ticks simulated
final_tick 100000000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_tick_rate 31243111314 # Simulator tick rate (ticks/s)
host_mem_usage 230668 # Number of bytes of host memory used
host_seconds 3.20 # Real time elapsed on the host
host_tick_rate 15527580566 # Simulator tick rate (ticks/s)
host_mem_usage 226756 # Number of bytes of host memory used
host_seconds 6.44 # Real time elapsed on the host
system.physmem.bytes_read::cpu 64 # Number of bytes read from this memory
system.physmem.bytes_read::total 64 # Number of bytes read from this memory
system.physmem.bytes_written::cpu 213335552 # Number of bytes written to this memory
@@ -151,9 +151,9 @@ system.monitor.readLatencyHist::36864-38911 0 0.00% 100.00% #
system.monitor.readLatencyHist::38912-40959 0 0.00% 100.00% # Read request-response latency
system.monitor.readLatencyHist::total 1 # Read request-response latency
system.monitor.writeLatencyHist::samples 3333367 # Write request-response latency
system.monitor.writeLatencyHist::mean 30000 # Write request-response latency
system.monitor.writeLatencyHist::gmean 29999.999984 # Write request-response latency
system.monitor.writeLatencyHist::stdev 0 # Write request-response latency
system.monitor.writeLatencyHist::mean 30000.000098 # Write request-response latency
system.monitor.writeLatencyHist::gmean 30000.000081 # Write request-response latency
system.monitor.writeLatencyHist::stdev 0.179652 # Write request-response latency
system.monitor.writeLatencyHist::0-2047 0 0.00% 0.00% # Write request-response latency
system.monitor.writeLatencyHist::2048-4095 0 0.00% 0.00% # Write request-response latency
system.monitor.writeLatencyHist::4096-6143 0 0.00% 0.00% # Write request-response latency
@@ -204,8 +204,8 @@ system.monitor.ittReadRead::min_value 0 # Re
system.monitor.ittReadRead::max_value 0 # Read-to-read inter transaction time
system.monitor.ittReadRead::total 0 # Read-to-read inter transaction time
system.monitor.ittWriteWrite::samples 3333367 # Write-to-write inter transaction time
system.monitor.ittWriteWrite::mean 29999.695203 # Write-to-write inter transaction time
system.monitor.ittWriteWrite::stdev 539.134360 # Write-to-write inter transaction time
system.monitor.ittWriteWrite::mean 29999.695301 # Write-to-write inter transaction time
system.monitor.ittWriteWrite::stdev 539.310304 # Write-to-write inter transaction time
system.monitor.ittWriteWrite::underflows 0 0.00% 0.00% # Write-to-write inter transaction time
system.monitor.ittWriteWrite::1-5000 0 0.00% 0.00% # Write-to-write inter transaction time
system.monitor.ittWriteWrite::5001-10000 99 0.00% 0.00% # Write-to-write inter transaction time
@@ -229,11 +229,11 @@ system.monitor.ittWriteWrite::90001-95000 0 0.00% 100.00% # W
system.monitor.ittWriteWrite::95001-100000 0 0.00% 100.00% # Write-to-write inter transaction time
system.monitor.ittWriteWrite::overflows 1 0.00% 100.00% # Write-to-write inter transaction time
system.monitor.ittWriteWrite::min_value 10000 # Write-to-write inter transaction time
system.monitor.ittWriteWrite::max_value 994000 # Write-to-write inter transaction time
system.monitor.ittWriteWrite::max_value 994328 # Write-to-write inter transaction time
system.monitor.ittWriteWrite::total 3333367 # Write-to-write inter transaction time
system.monitor.ittReqReq::samples 3333368 # Request-to-request inter transaction time
system.monitor.ittReqReq::mean 29999.687703 # Request-to-request inter transaction time
system.monitor.ittReqReq::stdev 539.308135 # Request-to-request inter transaction time
system.monitor.ittReqReq::stdev 539.488612 # Request-to-request inter transaction time
system.monitor.ittReqReq::underflows 0 0.00% 0.00% # Request-to-request inter transaction time
system.monitor.ittReqReq::1-5000 1 0.00% 0.00% # Request-to-request inter transaction time
system.monitor.ittReqReq::5001-10000 99 0.00% 0.00% # Request-to-request inter transaction time
@@ -256,8 +256,8 @@ system.monitor.ittReqReq::85001-90000 0 0.00% 100.00% # Re
system.monitor.ittReqReq::90001-95000 0 0.00% 100.00% # Request-to-request inter transaction time
system.monitor.ittReqReq::95001-100000 0 0.00% 100.00% # Request-to-request inter transaction time
system.monitor.ittReqReq::overflows 1 0.00% 100.00% # Request-to-request inter transaction time
system.monitor.ittReqReq::min_value 5000 # Request-to-request inter transaction time
system.monitor.ittReqReq::max_value 994000 # Request-to-request inter transaction time
system.monitor.ittReqReq::min_value 4672 # Request-to-request inter transaction time
system.monitor.ittReqReq::max_value 994328 # Request-to-request inter transaction time
system.monitor.ittReqReq::total 3333368 # Request-to-request inter transaction time
system.monitor.outstandingReadsHist::samples 100 # Outstanding read transactions
system.monitor.outstandingReadsHist::mean 0 # Outstanding read transactions