diff --git a/src/arch/riscv/isa/formats/vector_arith.isa b/src/arch/riscv/isa/formats/vector_arith.isa
index 1ddf323f04..7f87f1e163 100644
--- a/src/arch/riscv/isa/formats/vector_arith.isa
+++ b/src/arch/riscv/isa/formats/vector_arith.isa
@@ -1049,7 +1049,7 @@ def format Vector1Vs1VdMaskFormat(code, category, *flags){{
          },
         flags)
 
-    header_output = Vector1Vs1RdMaskDeclare.subst(iop)
+    header_output = Vector1Vs1VdMaskDeclare.subst(iop)
     decoder_output = Vector1Vs1VdMaskConstructor.subst(iop)
     exec_output = Vector1Vs1VdMaskExecute.subst(iop)
     decode_block = VectorMaskDecodeBlock.subst(iop)
diff --git a/src/arch/riscv/isa/templates/vector_arith.isa b/src/arch/riscv/isa/templates/vector_arith.isa
index 12eab95246..c808f08ee4 100644
--- a/src/arch/riscv/isa/templates/vector_arith.isa
+++ b/src/arch/riscv/isa/templates/vector_arith.isa
@@ -951,6 +951,21 @@ Fault
 
 }};
 
+def template Vector1Vs1VdMaskDeclare {{
+
+template<typename ElemType>
+class %(class_name)s : public %(base_class)s {
+private:
+    RegId srcRegIdxArr[3];
+    RegId destRegIdxArr[1];
+    bool vm;
+public:
+    %(class_name)s(ExtMachInst _machInst);
+    Fault execute(ExecContext* xc, trace::InstRecord* traceData)const override;
+    using %(base_class)s::generateDisassembly;
+};
+
+}};
 
 def template Vector1Vs1VdMaskConstructor {{