Stats: Re update stats.
This commit is contained in:
Gabe Black
@@ -1,13 +1,22 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
dummy=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
mem_mode=atomic
|
||||
physmem=system.physmem
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
|
||||
[system.cpu]
|
||||
type=InOrderCPU
|
||||
@@ -192,7 +201,7 @@ egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=tests/test-progs/hello/bin/alpha/linux/hello
|
||||
executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
||||
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jan 24 2011 18:18:02
|
||||
M5 revision 09e8ac96522d+ 7823+ default regression_updates qtip tip
|
||||
M5 started Jan 24 2011 18:18:03
|
||||
M5 executing on zooks
|
||||
M5 compiled Feb 7 2011 01:47:18
|
||||
M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
|
||||
M5 started Feb 7 2011 01:47:37
|
||||
M5 executing on burrito
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/inorder-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
@@ -1,9 +1,9 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 36108 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 155860 # Number of bytes of host memory used
|
||||
host_seconds 0.18 # Real time elapsed on the host
|
||||
host_tick_rate 125462283 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 37548 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 223436 # Number of bytes of host memory used
|
||||
host_seconds 0.17 # Real time elapsed on the host
|
||||
host_tick_rate 130476959 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 6404 # Number of instructions simulated
|
||||
sim_seconds 0.000022 # Number of seconds simulated
|
||||
@@ -267,6 +267,8 @@ system.cpu.l2cache.total_refs 1 # To
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||
system.cpu.numCycles 44578 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.runCycles 7154 # Number of cycles cpu stages are processed.
|
||||
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread)
|
||||
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
|
||||
|
||||
@@ -1,13 +1,22 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
dummy=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
mem_mode=atomic
|
||||
physmem=system.physmem
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
|
||||
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jan 17 2011 16:24:53
|
||||
M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase
|
||||
M5 started Jan 17 2011 16:24:57
|
||||
M5 executing on zizzer
|
||||
M5 compiled Feb 7 2011 01:47:18
|
||||
M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
|
||||
M5 started Feb 7 2011 01:47:37
|
||||
M5 executing on burrito
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
@@ -1,9 +1,9 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 10121 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 203516 # Number of bytes of host memory used
|
||||
host_seconds 0.63 # Real time elapsed on the host
|
||||
host_tick_rate 19665204 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 34686 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 223912 # Number of bytes of host memory used
|
||||
host_seconds 0.18 # Real time elapsed on the host
|
||||
host_tick_rate 67319594 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 6386 # Number of instructions simulated
|
||||
sim_seconds 0.000012 # Number of seconds simulated
|
||||
@@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value 0
|
||||
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::total 12265 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:count 6403 # Number of instructions committed
|
||||
system.cpu.commit.COM:fp_insts 10 # Number of committed floating point instructions.
|
||||
system.cpu.commit.COM:function_calls 127 # Number of function calls committed.
|
||||
system.cpu.commit.COM:int_insts 6321 # Number of committed integer instructions.
|
||||
system.cpu.commit.COM:loads 1185 # Number of loads committed
|
||||
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
|
||||
system.cpu.commit.COM:refs 2050 # Number of memory references committed
|
||||
@@ -169,6 +172,8 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 13149 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fp_regfile_reads 8 # number of floating regfile reads
|
||||
system.cpu.fp_regfile_writes 2 # number of floating regfile writes
|
||||
system.cpu.icache.ReadReq_accesses 1774 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 35292.253521 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35283.387622 # average ReadReq mshr miss latency
|
||||
@@ -268,6 +273,8 @@ system.cpu.iew.lsq.thread.0.squashedStores 394 #
|
||||
system.cpu.iew.memOrderViolationEvents 63 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 303 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 125 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.int_regfile_reads 11489 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 6462 # number of integer regfile writes
|
||||
system.cpu.ipc 0.257230 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.257230 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued
|
||||
@@ -359,6 +366,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value 0
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::total 13149 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:rate 0.373520 # Inst issue rate
|
||||
system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes
|
||||
system.cpu.iq.int_alu_accesses 9351 # Number of integer alu accesses
|
||||
system.cpu.iq.int_inst_queue_reads 31807 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 8672 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.int_inst_queue_writes 14983 # Number of integer instruction queue writes
|
||||
system.cpu.iq.iqInstsAdded 10848 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 9273 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 25 # Number of non-speculative instructions added to the IQ
|
||||
@@ -450,7 +465,11 @@ system.cpu.memDep0.conflictingLoads 34 # Nu
|
||||
system.cpu.memDep0.conflictingStores 26 # Number of conflicting stores.
|
||||
system.cpu.memDep0.insertedLoads 2242 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 1259 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.misc_regfile_reads 1 # number of misc regfile reads
|
||||
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
|
||||
system.cpu.numCycles 24826 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.rename.RENAME:BlockCycles 346 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:CommittedMaps 4583 # Number of HB maps that are committed
|
||||
system.cpu.rename.RENAME:IQFullEvents 8 # Number of times rename has blocked due to IQ full
|
||||
@@ -463,10 +482,14 @@ system.cpu.rename.RENAME:RunCycles 2180 # Nu
|
||||
system.cpu.rename.RENAME:SquashCycles 884 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 270 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 4300 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:fp_rename_lookups 17 # Number of floating rename lookups
|
||||
system.cpu.rename.RENAME:int_rename_lookups 15016 # Number of integer rename lookups
|
||||
system.cpu.rename.RENAME:serializeStallCycles 406 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 28 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 694 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 22 # count of temporary serializing insts renamed
|
||||
system.cpu.rob.rob_reads 22718 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 22732 # The number of ROB writes
|
||||
system.cpu.timesIdled 239 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
|
||||
|
||||
|
||||
@@ -1,13 +1,22 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
dummy=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
mem_mode=atomic
|
||||
physmem=system.physmem
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
|
||||
[system.cpu]
|
||||
type=AtomicSimpleCPU
|
||||
@@ -57,7 +66,7 @@ egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello
|
||||
executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
||||
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Feb 24 2010 23:12:40
|
||||
M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
|
||||
M5 started Feb 25 2010 03:01:37
|
||||
M5 executing on SC2B0619
|
||||
M5 compiled Feb 7 2011 01:47:18
|
||||
M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
|
||||
M5 started Feb 7 2011 01:47:39
|
||||
M5 executing on burrito
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
@@ -1,9 +1,9 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 1228467 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 182556 # Number of bytes of host memory used
|
||||
host_inst_rate 474100 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 215244 # Number of bytes of host memory used
|
||||
host_seconds 0.01 # Real time elapsed on the host
|
||||
host_tick_rate 587751371 # Simulator tick rate (ticks/s)
|
||||
host_tick_rate 233713954 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 6404 # Number of instructions simulated
|
||||
sim_seconds 0.000003 # Number of seconds simulated
|
||||
@@ -43,8 +43,24 @@ system.cpu.itb.write_hits 0 # DT
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 6431 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.num_busy_cycles 6431 # Number of busy cycles
|
||||
system.cpu.num_conditional_control_insts 750 # number of instructions that are conditional controls
|
||||
system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
|
||||
system.cpu.num_fp_insts 10 # number of float instructions
|
||||
system.cpu.num_fp_register_reads 8 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
|
||||
system.cpu.num_func_calls 251 # number of times a function call or return occured
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_insts 6404 # Number of instructions executed
|
||||
system.cpu.num_refs 2060 # Number of memory references
|
||||
system.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses
|
||||
system.cpu.num_int_insts 6331 # number of integer instructions
|
||||
system.cpu.num_int_register_reads 8304 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 4581 # number of times the integer registers were written
|
||||
system.cpu.num_load_insts 1192 # Number of load instructions
|
||||
system.cpu.num_mem_refs 2060 # number of memory refs
|
||||
system.cpu.num_store_insts 868 # Number of store instructions
|
||||
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
||||
@@ -1,13 +1,22 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
dummy=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000
|
||||
time_sync_spin_threshold=100000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu physmem ruby
|
||||
children=cpu dir_cntrl0 l1_cntrl0 physmem ruby
|
||||
mem_mode=timing
|
||||
physmem=system.physmem
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
@@ -32,8 +41,8 @@ progress_interval=0
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[1]
|
||||
icache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0]
|
||||
dcache_port=system.ruby.cpu_ruby_ports.port[1]
|
||||
icache_port=system.ruby.cpu_ruby_ports.port[0]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=AlphaTLB
|
||||
@@ -54,7 +63,7 @@ egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=tests/test-progs/hello/bin/alpha/linux/hello
|
||||
executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
@@ -65,126 +74,27 @@ simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
latency=30
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort
|
||||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
children=debug network profiler tracer
|
||||
block_size_bytes=64
|
||||
clock=1
|
||||
debug=system.ruby.debug
|
||||
mem_size=134217728
|
||||
network=system.ruby.network
|
||||
profiler=system.ruby.profiler
|
||||
random_seed=1234
|
||||
randomization=false
|
||||
stats_filename=ruby.stats
|
||||
tracer=system.ruby.tracer
|
||||
|
||||
[system.ruby.debug]
|
||||
type=RubyDebug
|
||||
filter_string=none
|
||||
output_filename=none
|
||||
protocol_trace=false
|
||||
start_time=1
|
||||
verbosity_string=none
|
||||
|
||||
[system.ruby.network]
|
||||
type=SimpleNetwork
|
||||
children=topology
|
||||
adaptive_routing=true
|
||||
buffer_size=0
|
||||
control_msg_size=8
|
||||
endpoint_bandwidth=10000
|
||||
link_latency=1
|
||||
number_of_virtual_networks=10
|
||||
topology=system.ruby.network.topology
|
||||
|
||||
[system.ruby.network.topology]
|
||||
type=Topology
|
||||
children=ext_links0 ext_links1 int_links0 int_links1
|
||||
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1
|
||||
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1
|
||||
num_int_nodes=3
|
||||
print_config=false
|
||||
|
||||
[system.ruby.network.topology.ext_links0]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links0.ext_node
|
||||
int_node=0
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=sequencer
|
||||
buffer_size=0
|
||||
cacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
cache_response_latency=12
|
||||
issue_latency=2
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.sequencer]
|
||||
type=RubySequencer
|
||||
children=icache
|
||||
dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
physMemPort=system.physmem.port[0]
|
||||
port=system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links1]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links1.ext_node
|
||||
int_node=1
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node]
|
||||
[system.dir_cntrl0]
|
||||
type=Directory_Controller
|
||||
children=directory memBuffer
|
||||
buffer_size=0
|
||||
directory=system.ruby.network.topology.ext_links1.ext_node.directory
|
||||
directory=system.dir_cntrl0.directory
|
||||
directory_latency=12
|
||||
memBuffer=system.ruby.network.topology.ext_links1.ext_node.memBuffer
|
||||
memBuffer=system.dir_cntrl0.memBuffer
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node.directory]
|
||||
[system.dir_cntrl0.directory]
|
||||
type=RubyDirectoryMemory
|
||||
map_levels=4
|
||||
numa_high_bit=6
|
||||
size=134217728
|
||||
use_map=false
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node.memBuffer]
|
||||
[system.dir_cntrl0.memBuffer]
|
||||
type=RubyMemoryControl
|
||||
bank_bit_0=8
|
||||
bank_busy_time=11
|
||||
@@ -205,6 +115,100 @@ refresh_period=1560
|
||||
tFaw=0
|
||||
version=0
|
||||
|
||||
[system.l1_cntrl0]
|
||||
type=L1Cache_Controller
|
||||
buffer_size=0
|
||||
cacheMemory=system.ruby.cpu_ruby_ports.dcache
|
||||
cache_response_latency=12
|
||||
issue_latency=2
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.ruby.cpu_ruby_ports
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
latency=30
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.ruby.cpu_ruby_ports.physMemPort
|
||||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
children=cpu_ruby_ports network profiler tracer
|
||||
block_size_bytes=64
|
||||
clock=1
|
||||
mem_size=134217728
|
||||
network=system.ruby.network
|
||||
no_mem_vec=false
|
||||
profiler=system.ruby.profiler
|
||||
random_seed=1234
|
||||
randomization=false
|
||||
stats_filename=ruby.stats
|
||||
tracer=system.ruby.tracer
|
||||
|
||||
[system.ruby.cpu_ruby_ports]
|
||||
type=RubySequencer
|
||||
children=dcache
|
||||
access_phys_mem=true
|
||||
dcache=system.ruby.cpu_ruby_ports.dcache
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.cpu_ruby_ports.dcache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
physMemPort=system.physmem.port[0]
|
||||
port=system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
[system.ruby.cpu_ruby_ports.dcache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.ruby.network]
|
||||
type=SimpleNetwork
|
||||
children=topology
|
||||
adaptive_routing=false
|
||||
buffer_size=0
|
||||
control_msg_size=8
|
||||
endpoint_bandwidth=10000
|
||||
link_latency=1
|
||||
number_of_virtual_networks=10
|
||||
topology=system.ruby.network.topology
|
||||
|
||||
[system.ruby.network.topology]
|
||||
type=Topology
|
||||
children=ext_links0 ext_links1 int_links0 int_links1
|
||||
description=Crossbar
|
||||
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1
|
||||
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1
|
||||
num_int_nodes=3
|
||||
print_config=false
|
||||
|
||||
[system.ruby.network.topology.ext_links0]
|
||||
type=ExtLink
|
||||
bw_multiplier=64
|
||||
ext_node=system.l1_cntrl0
|
||||
int_node=0
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links1]
|
||||
type=ExtLink
|
||||
bw_multiplier=64
|
||||
ext_node=system.dir_cntrl0
|
||||
int_node=1
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.int_links0]
|
||||
type=IntLink
|
||||
bw_multiplier=16
|
||||
|
||||
@@ -18,9 +18,9 @@ topology:
|
||||
virtual_net_0: active, ordered
|
||||
virtual_net_1: active, ordered
|
||||
virtual_net_2: active, ordered
|
||||
virtual_net_3: inactive
|
||||
virtual_net_3: active, ordered
|
||||
virtual_net_4: active, ordered
|
||||
virtual_net_5: active, ordered
|
||||
virtual_net_5: inactive
|
||||
virtual_net_6: inactive
|
||||
virtual_net_7: inactive
|
||||
virtual_net_8: inactive
|
||||
@@ -34,7 +34,7 @@ periodic_stats_period: 1000000
|
||||
================ End RubySystem Configuration Print ================
|
||||
|
||||
|
||||
Real time: Jan/28/2010 10:15:29
|
||||
Real time: Feb/07/2011 01:47:49
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
@@ -43,31 +43,20 @@ Elapsed_time_in_minutes: 0.0166667
|
||||
Elapsed_time_in_hours: 0.000277778
|
||||
Elapsed_time_in_days: 1.15741e-05
|
||||
|
||||
Virtual_time_in_seconds: 0.5
|
||||
Virtual_time_in_minutes: 0.00833333
|
||||
Virtual_time_in_hours: 0.000138889
|
||||
Virtual_time_in_days: 5.78704e-06
|
||||
Virtual_time_in_seconds: 0.35
|
||||
Virtual_time_in_minutes: 0.00583333
|
||||
Virtual_time_in_hours: 9.72222e-05
|
||||
Virtual_time_in_days: 4.05093e-06
|
||||
|
||||
Ruby_current_time: 342698
|
||||
Ruby_start_time: 0
|
||||
Ruby_cycles: 342698
|
||||
|
||||
mbytes_resident: 34.2148
|
||||
mbytes_total: 34.2227
|
||||
resident_ratio: 1
|
||||
|
||||
Total_misses: 0
|
||||
total_misses: 0 [ 0 ]
|
||||
user_misses: 0 [ 0 ]
|
||||
supervisor_misses: 0 [ 0 ]
|
||||
|
||||
ruby_cycles_executed: 342699 [ 342699 ]
|
||||
|
||||
transactions_started: 0 [ 0 ]
|
||||
transactions_ended: 0 [ 0 ]
|
||||
cycles_per_transaction: 0 [ 0 ]
|
||||
misses_per_transaction: 0 [ 0 ]
|
||||
mbytes_resident: 37.7383
|
||||
mbytes_total: 227.77
|
||||
resident_ratio: 0.165703
|
||||
|
||||
ruby_cycles_executed: [ 342699 ]
|
||||
|
||||
Busy Controller Counts:
|
||||
L1Cache-0:0
|
||||
@@ -81,9 +70,27 @@ sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8465 average: 1 |
|
||||
All Non-Zero Cycle Demand Cache Accesses
|
||||
----------------------------------------
|
||||
miss_latency: [binsize: 2 max: 377 count: 8464 average: 39.4889 | standard deviation: 72.9776 | 0 6734 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 6 1 3 6 0 334 211 182 529 243 4 4 0 5 2 15 9 4 14 10 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 30 18 15 24 37 2 3 0 0 2 2 1 1 3 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 ]
|
||||
miss_latency_1: [binsize: 2 max: 285 count: 6414 average: 23.2806 | standard deviation: 57.2661 | 0 5684 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 1 2 4 0 155 91 77 220 92 2 3 0 1 2 2 6 1 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 20 9 5 10 12 2 1 0 0 1 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_2: [binsize: 2 max: 375 count: 1185 average: 110.608 | standard deviation: 87.0282 | 0 458 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 3 0 1 2 0 147 90 74 255 81 2 1 0 3 0 12 3 1 9 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 4 2 11 4 0 2 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_3: [binsize: 2 max: 377 count: 865 average: 62.2439 | standard deviation: 89.6671 | 0 592 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32 30 31 54 70 0 0 0 1 0 1 0 2 2 4 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 5 8 3 21 0 0 0 0 0 0 0 1 2 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 ]
|
||||
miss_latency_IFETCH: [binsize: 2 max: 285 count: 6414 average: 23.2806 | standard deviation: 57.2661 | 0 5684 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 1 2 4 0 155 91 77 220 92 2 3 0 1 2 2 6 1 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 20 9 5 10 12 2 1 0 0 1 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_LD: [binsize: 2 max: 375 count: 1185 average: 110.608 | standard deviation: 87.0282 | 0 458 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 3 0 1 2 0 147 90 74 255 81 2 1 0 3 0 12 3 1 9 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 4 2 11 4 0 2 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST: [binsize: 2 max: 377 count: 865 average: 62.2439 | standard deviation: 89.6671 | 0 592 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32 30 31 54 70 0 0 0 1 0 1 0 2 2 4 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 5 8 3 21 0 0 0 0 0 0 0 1 2 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 ]
|
||||
miss_latency_L1Cache: [binsize: 1 max: 3 count: 6734 average: 3 | standard deviation: 0 | 0 0 0 6734 ]
|
||||
miss_latency_Directory: [binsize: 2 max: 377 count: 1730 average: 181.521 | standard deviation: 26.4115 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 6 1 3 6 0 334 211 182 529 243 4 4 0 5 2 15 9 4 14 10 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 30 18 15 24 37 2 3 0 0 2 2 1 1 3 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 ]
|
||||
miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
imcomplete_wCC_Times: 0
|
||||
miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
|
||||
miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
|
||||
miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
|
||||
miss_latency_dir_first_response_to_completion: [binsize: 1 max: 159 count: 1 average: 159 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
imcomplete_dir_Times: 1729
|
||||
miss_latency_IFETCH_L1Cache: [binsize: 1 max: 3 count: 5684 average: 3 | standard deviation: 0 | 0 0 0 5684 ]
|
||||
miss_latency_IFETCH_Directory: [binsize: 2 max: 285 count: 730 average: 181.192 | standard deviation: 25.9199 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 1 2 4 0 155 91 77 220 92 2 3 0 1 2 2 6 1 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 20 9 5 10 12 2 1 0 0 1 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_LD_L1Cache: [binsize: 1 max: 3 count: 458 average: 3 | standard deviation: 0 | 0 0 0 458 ]
|
||||
miss_latency_LD_Directory: [binsize: 2 max: 375 count: 727 average: 178.4 | standard deviation: 21.0913 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 3 0 1 2 0 147 90 74 255 81 2 1 0 3 0 12 3 1 9 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 4 2 11 4 0 2 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST_L1Cache: [binsize: 1 max: 3 count: 592 average: 3 | standard deviation: 0 | 0 0 0 592 ]
|
||||
miss_latency_ST_Directory: [binsize: 2 max: 377 count: 273 average: 190.714 | standard deviation: 36.5384 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32 30 31 54 70 0 0 0 1 0 1 0 2 2 4 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 5 8 3 21 0 0 0 0 0 0 0 1 2 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 ]
|
||||
|
||||
All Non-Zero Cycle SW Prefetch Requests
|
||||
------------------------------------
|
||||
@@ -115,25 +122,31 @@ Resource Usage
|
||||
page_size: 4096
|
||||
user_time: 0
|
||||
system_time: 0
|
||||
page_reclaims: 7357
|
||||
page_faults: 2195
|
||||
page_reclaims: 10742
|
||||
page_faults: 0
|
||||
swaps: 0
|
||||
block_inputs: 0
|
||||
block_outputs: 0
|
||||
block_outputs: 64
|
||||
|
||||
Network Stats
|
||||
-------------
|
||||
|
||||
total_msg_count_Control: 5190 41520
|
||||
total_msg_count_Data: 5178 372816
|
||||
total_msg_count_Response_Data: 5190 373680
|
||||
total_msg_count_Writeback_Control: 5178 41424
|
||||
total_msgs: 20736 total_bytes: 829440
|
||||
|
||||
switch_0_inlinks: 2
|
||||
switch_0_outlinks: 2
|
||||
links_utilized_percent_switch_0: 0.157486
|
||||
links_utilized_percent_switch_0_link_0: 0.0630876 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 0.251884 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_0_link_0_Response_Data: 1730 124560 [ 0 1730 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Writeback_Control: 1726 13808 [ 0 0 1726 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Control: 1730 13840 [ 1730 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Data: 1726 124272 [ 1726 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Response_Data: 1730 124560 [ 0 0 0 0 1730 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Writeback_Control: 1726 13808 [ 0 0 0 1726 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Control: 1730 13840 [ 0 0 1730 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Data: 1726 124272 [ 0 0 1726 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_1_inlinks: 2
|
||||
switch_1_outlinks: 2
|
||||
@@ -141,10 +154,10 @@ links_utilized_percent_switch_1: 0.157661
|
||||
links_utilized_percent_switch_1_link_0: 0.0629709 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 0.25235 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_1_link_0_Control: 1730 13840 [ 1730 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Data: 1726 124272 [ 1726 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Data: 1730 124560 [ 0 1730 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Writeback_Control: 1726 13808 [ 0 0 1726 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Control: 1730 13840 [ 0 0 1730 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Data: 1726 124272 [ 0 0 1726 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Data: 1730 124560 [ 0 0 0 0 1730 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Writeback_Control: 1726 13808 [ 0 0 0 1726 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_2_inlinks: 2
|
||||
switch_2_outlinks: 2
|
||||
@@ -152,66 +165,64 @@ links_utilized_percent_switch_2: 0.252117
|
||||
links_utilized_percent_switch_2_link_0: 0.25235 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 0.251884 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_2_link_0_Response_Data: 1730 124560 [ 0 1730 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Control: 1726 13808 [ 0 0 1726 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Control: 1730 13840 [ 1730 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Data: 1726 124272 [ 1726 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Response_Data: 1730 124560 [ 0 0 0 0 1730 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Control: 1726 13808 [ 0 0 0 1726 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Control: 1730 13840 [ 0 0 1730 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Data: 1726 124272 [ 0 0 1726 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 1730
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 1730
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_misses_per_transaction: inf
|
||||
Cache Stats: system.ruby.cpu_ruby_ports.dcache
|
||||
system.ruby.cpu_ruby_ports.dcache_total_misses: 1730
|
||||
system.ruby.cpu_ruby_ports.dcache_total_demand_misses: 1730
|
||||
system.ruby.cpu_ruby_ports.dcache_total_prefetches: 0
|
||||
system.ruby.cpu_ruby_ports.dcache_total_sw_prefetches: 0
|
||||
system.ruby.cpu_ruby_ports.dcache_total_hw_prefetches: 0
|
||||
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_LD: 42.0231%
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_ST: 15.7803%
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_IFETCH: 42.1965%
|
||||
system.ruby.cpu_ruby_ports.dcache_request_type_LD: 42.0231%
|
||||
system.ruby.cpu_ruby_ports.dcache_request_type_ST: 15.7803%
|
||||
system.ruby.cpu_ruby_ports.dcache_request_type_IFETCH: 42.1965%
|
||||
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_access_mode_type_SupervisorMode: 1730 100%
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 8 count: 1730 average: 6.00925 | standard deviation: 2.00058 | 0 0 0 0 861 0 0 0 869 ]
|
||||
system.ruby.cpu_ruby_ports.dcache_access_mode_type_SupervisorMode: 1730 100%
|
||||
|
||||
--- L1Cache 0 ---
|
||||
--- L1Cache ---
|
||||
- Event Counts -
|
||||
Load 1185
|
||||
Ifetch 6414
|
||||
Store 865
|
||||
Data 1730
|
||||
Fwd_GETX 0
|
||||
Inv 0
|
||||
Replacement 1726
|
||||
Writeback_Ack 1726
|
||||
Writeback_Nack 0
|
||||
Load [1185 ] 1185
|
||||
Ifetch [6414 ] 6414
|
||||
Store [865 ] 865
|
||||
Data [1730 ] 1730
|
||||
Fwd_GETX [0 ] 0
|
||||
Inv [0 ] 0
|
||||
Replacement [1726 ] 1726
|
||||
Writeback_Ack [1726 ] 1726
|
||||
Writeback_Nack [0 ] 0
|
||||
|
||||
- Transitions -
|
||||
I Load 727
|
||||
I Ifetch 730
|
||||
I Store 273
|
||||
I Inv 0 <--
|
||||
I Replacement 0 <--
|
||||
I Load [727 ] 727
|
||||
I Ifetch [730 ] 730
|
||||
I Store [273 ] 273
|
||||
I Inv [0 ] 0
|
||||
I Replacement [0 ] 0
|
||||
|
||||
II Writeback_Nack 0 <--
|
||||
II Writeback_Nack [0 ] 0
|
||||
|
||||
M Load 458
|
||||
M Ifetch 5684
|
||||
M Store 592
|
||||
M Fwd_GETX 0 <--
|
||||
M Inv 0 <--
|
||||
M Replacement 1726
|
||||
M Load [458 ] 458
|
||||
M Ifetch [5684 ] 5684
|
||||
M Store [592 ] 592
|
||||
M Fwd_GETX [0 ] 0
|
||||
M Inv [0 ] 0
|
||||
M Replacement [1726 ] 1726
|
||||
|
||||
MI Fwd_GETX 0 <--
|
||||
MI Inv 0 <--
|
||||
MI Writeback_Ack 1726
|
||||
MI Writeback_Nack 0 <--
|
||||
MI Fwd_GETX [0 ] 0
|
||||
MI Inv [0 ] 0
|
||||
MI Writeback_Ack [1726 ] 1726
|
||||
MI Writeback_Nack [0 ] 0
|
||||
|
||||
MII Fwd_GETX 0 <--
|
||||
MII Fwd_GETX [0 ] 0
|
||||
|
||||
IS Data 1457
|
||||
IS Data [1457 ] 1457
|
||||
|
||||
IM Data 273
|
||||
IM Data [273 ] 273
|
||||
|
||||
Memory controller: system.ruby.network.topology.ext_links1.ext_node.memBuffer:
|
||||
Memory controller: system.dir_cntrl0.memBuffer:
|
||||
memory_total_requests: 3456
|
||||
memory_reads: 1730
|
||||
memory_writes: 1726
|
||||
@@ -231,70 +242,69 @@ Memory controller: system.ruby.network.topology.ext_links1.ext_node.memBuffer:
|
||||
memory_stalls_for_read_read_turnaround: 0
|
||||
accesses_per_bank: 162 36 92 110 106 362 98 36 32 34 83 92 110 104 84 86 83 53 50 58 64 124 212 72 66 50 122 190 220 325 42 98
|
||||
|
||||
--- Directory 0 ---
|
||||
--- Directory ---
|
||||
- Event Counts -
|
||||
GETX 1730
|
||||
GETS 0
|
||||
PUTX 1726
|
||||
PUTX_NotOwner 0
|
||||
DMA_READ 0
|
||||
DMA_WRITE 0
|
||||
Memory_Data 1730
|
||||
Memory_Ack 1726
|
||||
GETX [1730 ] 1730
|
||||
GETS [0 ] 0
|
||||
PUTX [1726 ] 1726
|
||||
PUTX_NotOwner [0 ] 0
|
||||
DMA_READ [0 ] 0
|
||||
DMA_WRITE [0 ] 0
|
||||
Memory_Data [1730 ] 1730
|
||||
Memory_Ack [1726 ] 1726
|
||||
|
||||
- Transitions -
|
||||
I GETX 1730
|
||||
I PUTX_NotOwner 0 <--
|
||||
I DMA_READ 0 <--
|
||||
I DMA_WRITE 0 <--
|
||||
I GETX [1730 ] 1730
|
||||
I PUTX_NotOwner [0 ] 0
|
||||
I DMA_READ [0 ] 0
|
||||
I DMA_WRITE [0 ] 0
|
||||
|
||||
M GETX 0 <--
|
||||
M PUTX 1726
|
||||
M PUTX_NotOwner 0 <--
|
||||
M DMA_READ 0 <--
|
||||
M DMA_WRITE 0 <--
|
||||
M GETX [0 ] 0
|
||||
M PUTX [1726 ] 1726
|
||||
M PUTX_NotOwner [0 ] 0
|
||||
M DMA_READ [0 ] 0
|
||||
M DMA_WRITE [0 ] 0
|
||||
|
||||
M_DRD GETX 0 <--
|
||||
M_DRD PUTX 0 <--
|
||||
M_DRD GETX [0 ] 0
|
||||
M_DRD PUTX [0 ] 0
|
||||
|
||||
M_DWR GETX 0 <--
|
||||
M_DWR PUTX 0 <--
|
||||
M_DWR GETX [0 ] 0
|
||||
M_DWR PUTX [0 ] 0
|
||||
|
||||
M_DWRI GETX 0 <--
|
||||
M_DWRI Memory_Ack 0 <--
|
||||
M_DWRI GETX [0 ] 0
|
||||
M_DWRI Memory_Ack [0 ] 0
|
||||
|
||||
M_DRDI GETX 0 <--
|
||||
M_DRDI Memory_Ack 0 <--
|
||||
M_DRDI GETX [0 ] 0
|
||||
M_DRDI Memory_Ack [0 ] 0
|
||||
|
||||
IM GETX 0 <--
|
||||
IM GETS 0 <--
|
||||
IM PUTX 0 <--
|
||||
IM PUTX_NotOwner 0 <--
|
||||
IM DMA_READ 0 <--
|
||||
IM DMA_WRITE 0 <--
|
||||
IM Memory_Data 1730
|
||||
IM GETX [0 ] 0
|
||||
IM GETS [0 ] 0
|
||||
IM PUTX [0 ] 0
|
||||
IM PUTX_NotOwner [0 ] 0
|
||||
IM DMA_READ [0 ] 0
|
||||
IM DMA_WRITE [0 ] 0
|
||||
IM Memory_Data [1730 ] 1730
|
||||
|
||||
MI GETX 0 <--
|
||||
MI GETS 0 <--
|
||||
MI PUTX 0 <--
|
||||
MI PUTX_NotOwner 0 <--
|
||||
MI DMA_READ 0 <--
|
||||
MI DMA_WRITE 0 <--
|
||||
MI Memory_Ack 1726
|
||||
MI GETX [0 ] 0
|
||||
MI GETS [0 ] 0
|
||||
MI PUTX [0 ] 0
|
||||
MI PUTX_NotOwner [0 ] 0
|
||||
MI DMA_READ [0 ] 0
|
||||
MI DMA_WRITE [0 ] 0
|
||||
MI Memory_Ack [1726 ] 1726
|
||||
|
||||
ID GETX 0 <--
|
||||
ID GETS 0 <--
|
||||
ID PUTX 0 <--
|
||||
ID PUTX_NotOwner 0 <--
|
||||
ID DMA_READ 0 <--
|
||||
ID DMA_WRITE 0 <--
|
||||
ID Memory_Data 0 <--
|
||||
|
||||
ID_W GETX 0 <--
|
||||
ID_W GETS 0 <--
|
||||
ID_W PUTX 0 <--
|
||||
ID_W PUTX_NotOwner 0 <--
|
||||
ID_W DMA_READ 0 <--
|
||||
ID_W DMA_WRITE 0 <--
|
||||
ID_W Memory_Ack 0 <--
|
||||
ID GETX [0 ] 0
|
||||
ID GETS [0 ] 0
|
||||
ID PUTX [0 ] 0
|
||||
ID PUTX_NotOwner [0 ] 0
|
||||
ID DMA_READ [0 ] 0
|
||||
ID DMA_WRITE [0 ] 0
|
||||
ID Memory_Data [0 ] 0
|
||||
|
||||
ID_W GETX [0 ] 0
|
||||
ID_W GETS [0 ] 0
|
||||
ID_W PUTX [0 ] 0
|
||||
ID_W PUTX_NotOwner [0 ] 0
|
||||
ID_W DMA_READ [0 ] 0
|
||||
ID_W DMA_WRITE [0 ] 0
|
||||
ID_W Memory_Ack
|
||||
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jan 27 2010 22:23:20
|
||||
M5 revision 6068d4fc30d3+ 6931+ default qtip tip brad/rubycfg_regress_udpate
|
||||
M5 started Jan 28 2010 10:15:28
|
||||
M5 executing on svvint07
|
||||
M5 compiled Feb 7 2011 01:47:18
|
||||
M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
|
||||
M5 started Feb 7 2011 01:47:48
|
||||
M5 executing on burrito
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
@@ -1,9 +1,9 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 19405 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 215700 # Number of bytes of host memory used
|
||||
host_seconds 0.33 # Real time elapsed on the host
|
||||
host_tick_rate 1038428 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 16267 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 233240 # Number of bytes of host memory used
|
||||
host_seconds 0.39 # Real time elapsed on the host
|
||||
host_tick_rate 870027 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
sim_insts 6404 # Number of instructions simulated
|
||||
sim_seconds 0.000343 # Number of seconds simulated
|
||||
@@ -43,8 +43,24 @@ system.cpu.itb.write_hits 0 # DT
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 342698 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.num_busy_cycles 342698 # Number of busy cycles
|
||||
system.cpu.num_conditional_control_insts 750 # number of instructions that are conditional controls
|
||||
system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
|
||||
system.cpu.num_fp_insts 10 # number of float instructions
|
||||
system.cpu.num_fp_register_reads 8 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
|
||||
system.cpu.num_func_calls 251 # number of times a function call or return occured
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_insts 6404 # Number of instructions executed
|
||||
system.cpu.num_refs 2060 # Number of memory references
|
||||
system.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses
|
||||
system.cpu.num_int_insts 6331 # number of integer instructions
|
||||
system.cpu.num_int_register_reads 8304 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 4581 # number of times the integer registers were written
|
||||
system.cpu.num_load_insts 1192 # Number of load instructions
|
||||
system.cpu.num_mem_refs 2060 # number of memory refs
|
||||
system.cpu.num_store_insts 868 # Number of store instructions
|
||||
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
||||
@@ -1,13 +1,22 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
dummy=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
mem_mode=atomic
|
||||
physmem=system.physmem
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
|
||||
@@ -1,5 +1,3 @@
|
||||
Redirecting stdout to build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing/simout
|
||||
Redirecting stderr to build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing/simerr
|
||||
M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2008
|
||||
@@ -7,11 +5,11 @@ The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Aug 26 2010 11:51:59
|
||||
M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
|
||||
M5 started Aug 26 2010 11:59:22
|
||||
M5 executing on zizzer
|
||||
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing
|
||||
M5 compiled Feb 7 2011 01:47:18
|
||||
M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
|
||||
M5 started Feb 7 2011 01:47:37
|
||||
M5 executing on burrito
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
|
||||
@@ -1,9 +1,9 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 332796 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 204128 # Number of bytes of host memory used
|
||||
host_inst_rate 267933 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 222956 # Number of bytes of host memory used
|
||||
host_seconds 0.02 # Real time elapsed on the host
|
||||
host_tick_rate 1691799077 # Simulator tick rate (ticks/s)
|
||||
host_tick_rate 1366456557 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 6404 # Number of instructions simulated
|
||||
sim_seconds 0.000033 # Number of seconds simulated
|
||||
@@ -227,8 +227,24 @@ system.cpu.l2cache.warmup_cycle 0 # Cy
|
||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 66014 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.num_busy_cycles 66014 # Number of busy cycles
|
||||
system.cpu.num_conditional_control_insts 750 # number of instructions that are conditional controls
|
||||
system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
|
||||
system.cpu.num_fp_insts 10 # number of float instructions
|
||||
system.cpu.num_fp_register_reads 8 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
|
||||
system.cpu.num_func_calls 251 # number of times a function call or return occured
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_insts 6404 # Number of instructions executed
|
||||
system.cpu.num_refs 2060 # Number of memory references
|
||||
system.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses
|
||||
system.cpu.num_int_insts 6331 # number of integer instructions
|
||||
system.cpu.num_int_register_reads 8304 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 4581 # number of times the integer registers were written
|
||||
system.cpu.num_load_insts 1192 # Number of load instructions
|
||||
system.cpu.num_mem_refs 2060 # number of memory refs
|
||||
system.cpu.num_store_insts 868 # Number of store instructions
|
||||
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
||||
@@ -1,13 +1,22 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
dummy=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
mem_mode=atomic
|
||||
physmem=system.physmem
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
|
||||
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jan 17 2011 16:24:53
|
||||
M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase
|
||||
M5 started Jan 17 2011 16:48:46
|
||||
M5 executing on zizzer
|
||||
M5 compiled Feb 7 2011 01:47:18
|
||||
M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
|
||||
M5 started Feb 7 2011 01:47:49
|
||||
M5 executing on burrito
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
@@ -1,9 +1,9 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 61982 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 202420 # Number of bytes of host memory used
|
||||
host_seconds 0.04 # Real time elapsed on the host
|
||||
host_tick_rate 188319059 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 33498 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 222808 # Number of bytes of host memory used
|
||||
host_seconds 0.07 # Real time elapsed on the host
|
||||
host_tick_rate 102057061 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 2387 # Number of instructions simulated
|
||||
sim_seconds 0.000007 # Number of seconds simulated
|
||||
@@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value 0
|
||||
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::total 6328 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:count 2576 # Number of instructions committed
|
||||
system.cpu.commit.COM:fp_insts 6 # Number of committed floating point instructions.
|
||||
system.cpu.commit.COM:function_calls 71 # Number of function calls committed.
|
||||
system.cpu.commit.COM:int_insts 2367 # Number of committed integer instructions.
|
||||
system.cpu.commit.COM:loads 415 # Number of loads committed
|
||||
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
|
||||
system.cpu.commit.COM:refs 709 # Number of memory references committed
|
||||
@@ -169,6 +172,7 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 6701 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fp_regfile_reads 6 # number of floating regfile reads
|
||||
system.cpu.icache.ReadReq_accesses 782 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 36074.786325 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35303.867403 # average ReadReq mshr miss latency
|
||||
@@ -268,6 +272,8 @@ system.cpu.iew.lsq.thread.0.squashedStores 141 #
|
||||
system.cpu.iew.memOrderViolationEvents 13 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 109 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 55 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.int_regfile_reads 4283 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 2601 # number of integer regfile writes
|
||||
system.cpu.ipc 0.163482 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.163482 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
||||
@@ -359,6 +365,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value 0
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::total 6701 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:rate 0.248682 # Inst issue rate
|
||||
system.cpu.iq.fp_alu_accesses 7 # Number of floating point alu accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes
|
||||
system.cpu.iq.int_alu_accesses 3659 # Number of integer alu accesses
|
||||
system.cpu.iq.int_inst_queue_reads 14008 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 3396 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.int_inst_queue_writes 5997 # Number of integer instruction queue writes
|
||||
system.cpu.iq.iqInstsAdded 4276 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 3631 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ
|
||||
@@ -449,7 +463,11 @@ system.cpu.memDep0.conflictingLoads 16 # Nu
|
||||
system.cpu.memDep0.conflictingStores 16 # Number of conflicting stores.
|
||||
system.cpu.memDep0.insertedLoads 793 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 435 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.misc_regfile_reads 1 # number of misc regfile reads
|
||||
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
|
||||
system.cpu.numCycles 14601 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.rename.RENAME:BlockCycles 63 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:CommittedMaps 1768 # Number of HB maps that are committed
|
||||
system.cpu.rename.RENAME:IQFullEvents 3 # Number of times rename has blocked due to IQ full
|
||||
@@ -462,10 +480,14 @@ system.cpu.rename.RENAME:RunCycles 901 # Nu
|
||||
system.cpu.rename.RENAME:SquashCycles 373 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 15 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 1713 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:fp_rename_lookups 12 # Number of floating rename lookups
|
||||
system.cpu.rename.RENAME:int_rename_lookups 5502 # Number of integer rename lookups
|
||||
system.cpu.rename.RENAME:serializeStallCycles 146 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 8 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 78 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 6 # count of temporary serializing insts renamed
|
||||
system.cpu.rob.rob_reads 10620 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 9524 # The number of ROB writes
|
||||
system.cpu.timesIdled 152 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.workload.PROG:num_syscalls 4 # Number of system calls
|
||||
|
||||
|
||||
@@ -1,13 +1,22 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
dummy=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
mem_mode=atomic
|
||||
physmem=system.physmem
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
|
||||
[system.cpu]
|
||||
type=AtomicSimpleCPU
|
||||
@@ -57,7 +66,7 @@ egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/chips/pd/randd/dist/test-progs/hello/bin/alpha/tru64/hello
|
||||
executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
||||
@@ -1,5 +1,3 @@
|
||||
Redirecting stdout to build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic/simout
|
||||
Redirecting stderr to build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic/simerr
|
||||
M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2008
|
||||
@@ -7,10 +5,10 @@ The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Nov 2 2010 21:30:55
|
||||
M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip
|
||||
M5 started Nov 2 2010 21:32:40
|
||||
M5 executing on aus-bc2-b15
|
||||
M5 compiled Feb 7 2011 01:47:18
|
||||
M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
|
||||
M5 started Feb 7 2011 01:47:37
|
||||
M5 executing on burrito
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
@@ -1,9 +1,9 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 759729 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 228516 # Number of bytes of host memory used
|
||||
host_seconds 0.00 # Real time elapsed on the host
|
||||
host_tick_rate 362937063 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 290762 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 214352 # Number of bytes of host memory used
|
||||
host_seconds 0.01 # Real time elapsed on the host
|
||||
host_tick_rate 142079814 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 2577 # Number of instructions simulated
|
||||
sim_seconds 0.000001 # Number of seconds simulated
|
||||
@@ -43,8 +43,24 @@ system.cpu.itb.write_hits 0 # DT
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 2596 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.num_busy_cycles 2596 # Number of busy cycles
|
||||
system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls
|
||||
system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses
|
||||
system.cpu.num_fp_insts 6 # number of float instructions
|
||||
system.cpu.num_fp_register_reads 6 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu.num_func_calls 140 # number of times a function call or return occured
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_insts 2577 # Number of instructions executed
|
||||
system.cpu.num_refs 717 # Number of memory references
|
||||
system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses
|
||||
system.cpu.num_int_insts 2375 # number of integer instructions
|
||||
system.cpu.num_int_register_reads 2998 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 1768 # number of times the integer registers were written
|
||||
system.cpu.num_load_insts 419 # Number of load instructions
|
||||
system.cpu.num_mem_refs 717 # number of memory refs
|
||||
system.cpu.num_store_insts 298 # Number of store instructions
|
||||
system.cpu.workload.PROG:num_syscalls 4 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
||||
@@ -1,13 +1,22 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
dummy=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000
|
||||
time_sync_spin_threshold=100000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu physmem ruby
|
||||
children=cpu dir_cntrl0 l1_cntrl0 physmem ruby
|
||||
mem_mode=timing
|
||||
physmem=system.physmem
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
@@ -32,8 +41,8 @@ progress_interval=0
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[1]
|
||||
icache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0]
|
||||
dcache_port=system.ruby.cpu_ruby_ports.port[1]
|
||||
icache_port=system.ruby.cpu_ruby_ports.port[0]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=AlphaTLB
|
||||
@@ -54,7 +63,7 @@ egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=tests/test-progs/hello/bin/alpha/tru64/hello
|
||||
executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
@@ -65,126 +74,27 @@ simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
latency=30
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort
|
||||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
children=debug network profiler tracer
|
||||
block_size_bytes=64
|
||||
clock=1
|
||||
debug=system.ruby.debug
|
||||
mem_size=134217728
|
||||
network=system.ruby.network
|
||||
profiler=system.ruby.profiler
|
||||
random_seed=1234
|
||||
randomization=false
|
||||
stats_filename=ruby.stats
|
||||
tracer=system.ruby.tracer
|
||||
|
||||
[system.ruby.debug]
|
||||
type=RubyDebug
|
||||
filter_string=none
|
||||
output_filename=none
|
||||
protocol_trace=false
|
||||
start_time=1
|
||||
verbosity_string=none
|
||||
|
||||
[system.ruby.network]
|
||||
type=SimpleNetwork
|
||||
children=topology
|
||||
adaptive_routing=true
|
||||
buffer_size=0
|
||||
control_msg_size=8
|
||||
endpoint_bandwidth=10000
|
||||
link_latency=1
|
||||
number_of_virtual_networks=10
|
||||
topology=system.ruby.network.topology
|
||||
|
||||
[system.ruby.network.topology]
|
||||
type=Topology
|
||||
children=ext_links0 ext_links1 int_links0 int_links1
|
||||
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1
|
||||
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1
|
||||
num_int_nodes=3
|
||||
print_config=false
|
||||
|
||||
[system.ruby.network.topology.ext_links0]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links0.ext_node
|
||||
int_node=0
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=sequencer
|
||||
buffer_size=0
|
||||
cacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
cache_response_latency=12
|
||||
issue_latency=2
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.sequencer]
|
||||
type=RubySequencer
|
||||
children=icache
|
||||
dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
physMemPort=system.physmem.port[0]
|
||||
port=system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links1]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links1.ext_node
|
||||
int_node=1
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node]
|
||||
[system.dir_cntrl0]
|
||||
type=Directory_Controller
|
||||
children=directory memBuffer
|
||||
buffer_size=0
|
||||
directory=system.ruby.network.topology.ext_links1.ext_node.directory
|
||||
directory=system.dir_cntrl0.directory
|
||||
directory_latency=12
|
||||
memBuffer=system.ruby.network.topology.ext_links1.ext_node.memBuffer
|
||||
memBuffer=system.dir_cntrl0.memBuffer
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node.directory]
|
||||
[system.dir_cntrl0.directory]
|
||||
type=RubyDirectoryMemory
|
||||
map_levels=4
|
||||
numa_high_bit=6
|
||||
size=134217728
|
||||
use_map=false
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node.memBuffer]
|
||||
[system.dir_cntrl0.memBuffer]
|
||||
type=RubyMemoryControl
|
||||
bank_bit_0=8
|
||||
bank_busy_time=11
|
||||
@@ -205,6 +115,100 @@ refresh_period=1560
|
||||
tFaw=0
|
||||
version=0
|
||||
|
||||
[system.l1_cntrl0]
|
||||
type=L1Cache_Controller
|
||||
buffer_size=0
|
||||
cacheMemory=system.ruby.cpu_ruby_ports.dcache
|
||||
cache_response_latency=12
|
||||
issue_latency=2
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.ruby.cpu_ruby_ports
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
latency=30
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.ruby.cpu_ruby_ports.physMemPort
|
||||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
children=cpu_ruby_ports network profiler tracer
|
||||
block_size_bytes=64
|
||||
clock=1
|
||||
mem_size=134217728
|
||||
network=system.ruby.network
|
||||
no_mem_vec=false
|
||||
profiler=system.ruby.profiler
|
||||
random_seed=1234
|
||||
randomization=false
|
||||
stats_filename=ruby.stats
|
||||
tracer=system.ruby.tracer
|
||||
|
||||
[system.ruby.cpu_ruby_ports]
|
||||
type=RubySequencer
|
||||
children=dcache
|
||||
access_phys_mem=true
|
||||
dcache=system.ruby.cpu_ruby_ports.dcache
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.cpu_ruby_ports.dcache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
physMemPort=system.physmem.port[0]
|
||||
port=system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
[system.ruby.cpu_ruby_ports.dcache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.ruby.network]
|
||||
type=SimpleNetwork
|
||||
children=topology
|
||||
adaptive_routing=false
|
||||
buffer_size=0
|
||||
control_msg_size=8
|
||||
endpoint_bandwidth=10000
|
||||
link_latency=1
|
||||
number_of_virtual_networks=10
|
||||
topology=system.ruby.network.topology
|
||||
|
||||
[system.ruby.network.topology]
|
||||
type=Topology
|
||||
children=ext_links0 ext_links1 int_links0 int_links1
|
||||
description=Crossbar
|
||||
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1
|
||||
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1
|
||||
num_int_nodes=3
|
||||
print_config=false
|
||||
|
||||
[system.ruby.network.topology.ext_links0]
|
||||
type=ExtLink
|
||||
bw_multiplier=64
|
||||
ext_node=system.l1_cntrl0
|
||||
int_node=0
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links1]
|
||||
type=ExtLink
|
||||
bw_multiplier=64
|
||||
ext_node=system.dir_cntrl0
|
||||
int_node=1
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.int_links0]
|
||||
type=IntLink
|
||||
bw_multiplier=16
|
||||
|
||||
@@ -18,9 +18,9 @@ topology:
|
||||
virtual_net_0: active, ordered
|
||||
virtual_net_1: active, ordered
|
||||
virtual_net_2: active, ordered
|
||||
virtual_net_3: inactive
|
||||
virtual_net_3: active, ordered
|
||||
virtual_net_4: active, ordered
|
||||
virtual_net_5: active, ordered
|
||||
virtual_net_5: inactive
|
||||
virtual_net_6: inactive
|
||||
virtual_net_7: inactive
|
||||
virtual_net_8: inactive
|
||||
@@ -34,40 +34,29 @@ periodic_stats_period: 1000000
|
||||
================ End RubySystem Configuration Print ================
|
||||
|
||||
|
||||
Real time: Jan/28/2010 10:26:06
|
||||
Real time: Feb/07/2011 01:47:37
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
Elapsed_time_in_seconds: 0
|
||||
Elapsed_time_in_minutes: 0
|
||||
Elapsed_time_in_hours: 0
|
||||
Elapsed_time_in_days: 0
|
||||
Elapsed_time_in_seconds: 1
|
||||
Elapsed_time_in_minutes: 0.0166667
|
||||
Elapsed_time_in_hours: 0.000277778
|
||||
Elapsed_time_in_days: 1.15741e-05
|
||||
|
||||
Virtual_time_in_seconds: 0.25
|
||||
Virtual_time_in_minutes: 0.00416667
|
||||
Virtual_time_in_hours: 6.94444e-05
|
||||
Virtual_time_in_days: 2.89352e-06
|
||||
Virtual_time_in_seconds: 0.26
|
||||
Virtual_time_in_minutes: 0.00433333
|
||||
Virtual_time_in_hours: 7.22222e-05
|
||||
Virtual_time_in_days: 3.00926e-06
|
||||
|
||||
Ruby_current_time: 123378
|
||||
Ruby_start_time: 0
|
||||
Ruby_cycles: 123378
|
||||
|
||||
mbytes_resident: 32.8828
|
||||
mbytes_total: 32.8906
|
||||
resident_ratio: 1
|
||||
|
||||
Total_misses: 0
|
||||
total_misses: 0 [ 0 ]
|
||||
user_misses: 0 [ 0 ]
|
||||
supervisor_misses: 0 [ 0 ]
|
||||
|
||||
ruby_cycles_executed: 123379 [ 123379 ]
|
||||
|
||||
transactions_started: 0 [ 0 ]
|
||||
transactions_ended: 0 [ 0 ]
|
||||
cycles_per_transaction: 0 [ 0 ]
|
||||
misses_per_transaction: 0 [ 0 ]
|
||||
mbytes_resident: 36.4062
|
||||
mbytes_total: 226.781
|
||||
resident_ratio: 0.160552
|
||||
|
||||
ruby_cycles_executed: [ 123379 ]
|
||||
|
||||
Busy Controller Counts:
|
||||
L1Cache-0:0
|
||||
@@ -81,9 +70,27 @@ sequencer_requests_outstanding: [binsize: 1 max: 1 count: 3295 average: 1 |
|
||||
All Non-Zero Cycle Demand Cache Accesses
|
||||
----------------------------------------
|
||||
miss_latency: [binsize: 2 max: 375 count: 3294 average: 36.4554 | standard deviation: 69.7725 | 0 2668 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 0 0 0 3 1 1 4 2 101 88 63 177 126 0 1 1 8 0 2 1 1 4 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 4 5 13 2 0 0 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_1: [binsize: 2 max: 375 count: 2585 average: 23.1702 | standard deviation: 56.4841 | 0 2288 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 0 0 2 2 31 53 29 71 82 0 1 0 5 0 1 1 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 2 1 3 2 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_2: [binsize: 2 max: 281 count: 415 average: 107.304 | standard deviation: 88.8453 | 0 170 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 2 0 56 24 27 75 32 0 0 1 3 0 1 0 0 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 0 4 7 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_3: [binsize: 2 max: 265 count: 294 average: 53.2585 | standard deviation: 80.456 | 0 210 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 14 11 7 31 12 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_IFETCH: [binsize: 2 max: 375 count: 2585 average: 23.1702 | standard deviation: 56.4841 | 0 2288 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 0 0 2 2 31 53 29 71 82 0 1 0 5 0 1 1 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 2 1 3 2 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_LD: [binsize: 2 max: 281 count: 415 average: 107.304 | standard deviation: 88.8453 | 0 170 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 2 0 56 24 27 75 32 0 0 1 3 0 1 0 0 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 0 4 7 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST: [binsize: 2 max: 265 count: 294 average: 53.2585 | standard deviation: 80.456 | 0 210 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 14 11 7 31 12 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_L1Cache: [binsize: 1 max: 3 count: 2668 average: 3 | standard deviation: 0 | 0 0 0 2668 ]
|
||||
miss_latency_Directory: [binsize: 2 max: 375 count: 626 average: 179.042 | standard deviation: 22.5462 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 0 0 0 3 1 1 4 2 101 88 63 177 126 0 1 1 8 0 2 1 1 4 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 4 5 13 2 0 0 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
imcomplete_wCC_Times: 0
|
||||
miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
|
||||
miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
|
||||
miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
|
||||
miss_latency_dir_first_response_to_completion: [binsize: 1 max: 159 count: 1 average: 159 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
imcomplete_dir_Times: 625
|
||||
miss_latency_IFETCH_L1Cache: [binsize: 1 max: 3 count: 2288 average: 3 | standard deviation: 0 | 0 0 0 2288 ]
|
||||
miss_latency_IFETCH_Directory: [binsize: 2 max: 375 count: 297 average: 178.556 | standard deviation: 21.9279 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 0 0 2 2 31 53 29 71 82 0 1 0 5 0 1 1 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 2 1 3 2 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_LD_L1Cache: [binsize: 1 max: 3 count: 170 average: 3 | standard deviation: 0 | 0 0 0 170 ]
|
||||
miss_latency_LD_Directory: [binsize: 2 max: 281 count: 245 average: 179.678 | standard deviation: 23.5327 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 2 0 56 24 27 75 32 0 0 1 3 0 1 0 0 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 0 4 7 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST_L1Cache: [binsize: 1 max: 3 count: 210 average: 3 | standard deviation: 0 | 0 0 0 210 ]
|
||||
miss_latency_ST_Directory: [binsize: 2 max: 265 count: 84 average: 178.905 | standard deviation: 21.977 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 14 11 7 31 12 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
|
||||
All Non-Zero Cycle SW Prefetch Requests
|
||||
------------------------------------
|
||||
@@ -115,25 +122,31 @@ Resource Usage
|
||||
page_size: 4096
|
||||
user_time: 0
|
||||
system_time: 0
|
||||
page_reclaims: 7118
|
||||
page_faults: 2103
|
||||
page_reclaims: 10395
|
||||
page_faults: 0
|
||||
swaps: 0
|
||||
block_inputs: 0
|
||||
block_outputs: 0
|
||||
block_outputs: 64
|
||||
|
||||
Network Stats
|
||||
-------------
|
||||
|
||||
total_msg_count_Control: 1878 15024
|
||||
total_msg_count_Data: 1866 134352
|
||||
total_msg_count_Response_Data: 1878 135216
|
||||
total_msg_count_Writeback_Control: 1866 14928
|
||||
total_msgs: 7488 total_bytes: 299520
|
||||
|
||||
switch_0_inlinks: 2
|
||||
switch_0_outlinks: 2
|
||||
links_utilized_percent_switch_0: 0.157808
|
||||
links_utilized_percent_switch_0_link_0: 0.0633825 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 0.252233 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_0_link_0_Response_Data: 626 45072 [ 0 626 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Writeback_Control: 622 4976 [ 0 0 622 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Control: 626 5008 [ 626 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Data: 622 44784 [ 622 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Response_Data: 626 45072 [ 0 0 0 0 626 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Writeback_Control: 622 4976 [ 0 0 0 622 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Control: 626 5008 [ 0 0 626 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Data: 622 44784 [ 0 0 622 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_1_inlinks: 2
|
||||
switch_1_outlinks: 2
|
||||
@@ -141,10 +154,10 @@ links_utilized_percent_switch_1: 0.158294
|
||||
links_utilized_percent_switch_1_link_0: 0.0630582 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 0.25353 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_1_link_0_Control: 626 5008 [ 626 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Data: 622 44784 [ 622 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Data: 626 45072 [ 0 626 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Writeback_Control: 622 4976 [ 0 0 622 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Control: 626 5008 [ 0 0 626 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Data: 622 44784 [ 0 0 622 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Data: 626 45072 [ 0 0 0 0 626 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Writeback_Control: 622 4976 [ 0 0 0 622 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_2_inlinks: 2
|
||||
switch_2_outlinks: 2
|
||||
@@ -152,66 +165,64 @@ links_utilized_percent_switch_2: 0.252881
|
||||
links_utilized_percent_switch_2_link_0: 0.25353 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 0.252233 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_2_link_0_Response_Data: 626 45072 [ 0 626 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Control: 622 4976 [ 0 0 622 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Control: 626 5008 [ 626 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Data: 622 44784 [ 622 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Response_Data: 626 45072 [ 0 0 0 0 626 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Control: 622 4976 [ 0 0 0 622 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Control: 626 5008 [ 0 0 626 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Data: 622 44784 [ 0 0 622 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 626
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 626
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_misses_per_transaction: inf
|
||||
Cache Stats: system.ruby.cpu_ruby_ports.dcache
|
||||
system.ruby.cpu_ruby_ports.dcache_total_misses: 626
|
||||
system.ruby.cpu_ruby_ports.dcache_total_demand_misses: 626
|
||||
system.ruby.cpu_ruby_ports.dcache_total_prefetches: 0
|
||||
system.ruby.cpu_ruby_ports.dcache_total_sw_prefetches: 0
|
||||
system.ruby.cpu_ruby_ports.dcache_total_hw_prefetches: 0
|
||||
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_LD: 39.1374%
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_ST: 13.4185%
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_IFETCH: 47.4441%
|
||||
system.ruby.cpu_ruby_ports.dcache_request_type_LD: 39.1374%
|
||||
system.ruby.cpu_ruby_ports.dcache_request_type_ST: 13.4185%
|
||||
system.ruby.cpu_ruby_ports.dcache_request_type_IFETCH: 47.4441%
|
||||
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_access_mode_type_SupervisorMode: 626 100%
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 8 count: 626 average: 5.71885 | standard deviation: 1.98192 | 0 0 0 0 357 0 0 0 269 ]
|
||||
system.ruby.cpu_ruby_ports.dcache_access_mode_type_SupervisorMode: 626 100%
|
||||
|
||||
--- L1Cache 0 ---
|
||||
--- L1Cache ---
|
||||
- Event Counts -
|
||||
Load 415
|
||||
Ifetch 2585
|
||||
Store 294
|
||||
Data 626
|
||||
Fwd_GETX 0
|
||||
Inv 0
|
||||
Replacement 622
|
||||
Writeback_Ack 622
|
||||
Writeback_Nack 0
|
||||
Load [415 ] 415
|
||||
Ifetch [2585 ] 2585
|
||||
Store [294 ] 294
|
||||
Data [626 ] 626
|
||||
Fwd_GETX [0 ] 0
|
||||
Inv [0 ] 0
|
||||
Replacement [622 ] 622
|
||||
Writeback_Ack [622 ] 622
|
||||
Writeback_Nack [0 ] 0
|
||||
|
||||
- Transitions -
|
||||
I Load 245
|
||||
I Ifetch 297
|
||||
I Store 84
|
||||
I Inv 0 <--
|
||||
I Replacement 0 <--
|
||||
I Load [245 ] 245
|
||||
I Ifetch [297 ] 297
|
||||
I Store [84 ] 84
|
||||
I Inv [0 ] 0
|
||||
I Replacement [0 ] 0
|
||||
|
||||
II Writeback_Nack 0 <--
|
||||
II Writeback_Nack [0 ] 0
|
||||
|
||||
M Load 170
|
||||
M Ifetch 2288
|
||||
M Store 210
|
||||
M Fwd_GETX 0 <--
|
||||
M Inv 0 <--
|
||||
M Replacement 622
|
||||
M Load [170 ] 170
|
||||
M Ifetch [2288 ] 2288
|
||||
M Store [210 ] 210
|
||||
M Fwd_GETX [0 ] 0
|
||||
M Inv [0 ] 0
|
||||
M Replacement [622 ] 622
|
||||
|
||||
MI Fwd_GETX 0 <--
|
||||
MI Inv 0 <--
|
||||
MI Writeback_Ack 622
|
||||
MI Writeback_Nack 0 <--
|
||||
MI Fwd_GETX [0 ] 0
|
||||
MI Inv [0 ] 0
|
||||
MI Writeback_Ack [622 ] 622
|
||||
MI Writeback_Nack [0 ] 0
|
||||
|
||||
MII Fwd_GETX 0 <--
|
||||
MII Fwd_GETX [0 ] 0
|
||||
|
||||
IS Data 542
|
||||
IS Data [542 ] 542
|
||||
|
||||
IM Data 84
|
||||
IM Data [84 ] 84
|
||||
|
||||
Memory controller: system.ruby.network.topology.ext_links1.ext_node.memBuffer:
|
||||
Memory controller: system.dir_cntrl0.memBuffer:
|
||||
memory_total_requests: 1248
|
||||
memory_reads: 626
|
||||
memory_writes: 622
|
||||
@@ -231,70 +242,69 @@ Memory controller: system.ruby.network.topology.ext_links1.ext_node.memBuffer:
|
||||
memory_stalls_for_read_read_turnaround: 0
|
||||
accesses_per_bank: 55 40 0 100 42 42 88 45 14 10 14 10 46 82 38 6 22 14 14 48 20 52 26 92 34 10 12 24 28 44 38 138
|
||||
|
||||
--- Directory 0 ---
|
||||
--- Directory ---
|
||||
- Event Counts -
|
||||
GETX 626
|
||||
GETS 0
|
||||
PUTX 622
|
||||
PUTX_NotOwner 0
|
||||
DMA_READ 0
|
||||
DMA_WRITE 0
|
||||
Memory_Data 626
|
||||
Memory_Ack 622
|
||||
GETX [626 ] 626
|
||||
GETS [0 ] 0
|
||||
PUTX [622 ] 622
|
||||
PUTX_NotOwner [0 ] 0
|
||||
DMA_READ [0 ] 0
|
||||
DMA_WRITE [0 ] 0
|
||||
Memory_Data [626 ] 626
|
||||
Memory_Ack [622 ] 622
|
||||
|
||||
- Transitions -
|
||||
I GETX 626
|
||||
I PUTX_NotOwner 0 <--
|
||||
I DMA_READ 0 <--
|
||||
I DMA_WRITE 0 <--
|
||||
I GETX [626 ] 626
|
||||
I PUTX_NotOwner [0 ] 0
|
||||
I DMA_READ [0 ] 0
|
||||
I DMA_WRITE [0 ] 0
|
||||
|
||||
M GETX 0 <--
|
||||
M PUTX 622
|
||||
M PUTX_NotOwner 0 <--
|
||||
M DMA_READ 0 <--
|
||||
M DMA_WRITE 0 <--
|
||||
M GETX [0 ] 0
|
||||
M PUTX [622 ] 622
|
||||
M PUTX_NotOwner [0 ] 0
|
||||
M DMA_READ [0 ] 0
|
||||
M DMA_WRITE [0 ] 0
|
||||
|
||||
M_DRD GETX 0 <--
|
||||
M_DRD PUTX 0 <--
|
||||
M_DRD GETX [0 ] 0
|
||||
M_DRD PUTX [0 ] 0
|
||||
|
||||
M_DWR GETX 0 <--
|
||||
M_DWR PUTX 0 <--
|
||||
M_DWR GETX [0 ] 0
|
||||
M_DWR PUTX [0 ] 0
|
||||
|
||||
M_DWRI GETX 0 <--
|
||||
M_DWRI Memory_Ack 0 <--
|
||||
M_DWRI GETX [0 ] 0
|
||||
M_DWRI Memory_Ack [0 ] 0
|
||||
|
||||
M_DRDI GETX 0 <--
|
||||
M_DRDI Memory_Ack 0 <--
|
||||
M_DRDI GETX [0 ] 0
|
||||
M_DRDI Memory_Ack [0 ] 0
|
||||
|
||||
IM GETX 0 <--
|
||||
IM GETS 0 <--
|
||||
IM PUTX 0 <--
|
||||
IM PUTX_NotOwner 0 <--
|
||||
IM DMA_READ 0 <--
|
||||
IM DMA_WRITE 0 <--
|
||||
IM Memory_Data 626
|
||||
IM GETX [0 ] 0
|
||||
IM GETS [0 ] 0
|
||||
IM PUTX [0 ] 0
|
||||
IM PUTX_NotOwner [0 ] 0
|
||||
IM DMA_READ [0 ] 0
|
||||
IM DMA_WRITE [0 ] 0
|
||||
IM Memory_Data [626 ] 626
|
||||
|
||||
MI GETX 0 <--
|
||||
MI GETS 0 <--
|
||||
MI PUTX 0 <--
|
||||
MI PUTX_NotOwner 0 <--
|
||||
MI DMA_READ 0 <--
|
||||
MI DMA_WRITE 0 <--
|
||||
MI Memory_Ack 622
|
||||
MI GETX [0 ] 0
|
||||
MI GETS [0 ] 0
|
||||
MI PUTX [0 ] 0
|
||||
MI PUTX_NotOwner [0 ] 0
|
||||
MI DMA_READ [0 ] 0
|
||||
MI DMA_WRITE [0 ] 0
|
||||
MI Memory_Ack [622 ] 622
|
||||
|
||||
ID GETX 0 <--
|
||||
ID GETS 0 <--
|
||||
ID PUTX 0 <--
|
||||
ID PUTX_NotOwner 0 <--
|
||||
ID DMA_READ 0 <--
|
||||
ID DMA_WRITE 0 <--
|
||||
ID Memory_Data 0 <--
|
||||
|
||||
ID_W GETX 0 <--
|
||||
ID_W GETS 0 <--
|
||||
ID_W PUTX 0 <--
|
||||
ID_W PUTX_NotOwner 0 <--
|
||||
ID_W DMA_READ 0 <--
|
||||
ID_W DMA_WRITE 0 <--
|
||||
ID_W Memory_Ack 0 <--
|
||||
ID GETX [0 ] 0
|
||||
ID GETS [0 ] 0
|
||||
ID PUTX [0 ] 0
|
||||
ID PUTX_NotOwner [0 ] 0
|
||||
ID DMA_READ [0 ] 0
|
||||
ID DMA_WRITE [0 ] 0
|
||||
ID Memory_Data [0 ] 0
|
||||
|
||||
ID_W GETX [0 ] 0
|
||||
ID_W GETS [0 ] 0
|
||||
ID_W PUTX [0 ] 0
|
||||
ID_W PUTX_NotOwner [0 ] 0
|
||||
ID_W DMA_READ [0 ] 0
|
||||
ID_W DMA_WRITE [0 ] 0
|
||||
ID_W Memory_Ack
|
||||
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jan 27 2010 22:23:20
|
||||
M5 revision 6068d4fc30d3+ 6931+ default qtip tip brad/rubycfg_regress_udpate
|
||||
M5 started Jan 28 2010 10:26:06
|
||||
M5 executing on svvint07
|
||||
M5 compiled Feb 7 2011 01:47:18
|
||||
M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
|
||||
M5 started Feb 7 2011 01:47:36
|
||||
M5 executing on burrito
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
@@ -1,9 +1,9 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 51538 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 214632 # Number of bytes of host memory used
|
||||
host_seconds 0.05 # Real time elapsed on the host
|
||||
host_tick_rate 2467461 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 17883 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 232228 # Number of bytes of host memory used
|
||||
host_seconds 0.14 # Real time elapsed on the host
|
||||
host_tick_rate 854675 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
sim_insts 2577 # Number of instructions simulated
|
||||
sim_seconds 0.000123 # Number of seconds simulated
|
||||
@@ -43,8 +43,24 @@ system.cpu.itb.write_hits 0 # DT
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 123378 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.num_busy_cycles 123378 # Number of busy cycles
|
||||
system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls
|
||||
system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses
|
||||
system.cpu.num_fp_insts 6 # number of float instructions
|
||||
system.cpu.num_fp_register_reads 6 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu.num_func_calls 140 # number of times a function call or return occured
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_insts 2577 # Number of instructions executed
|
||||
system.cpu.num_refs 717 # Number of memory references
|
||||
system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses
|
||||
system.cpu.num_int_insts 2375 # number of integer instructions
|
||||
system.cpu.num_int_register_reads 2998 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 1768 # number of times the integer registers were written
|
||||
system.cpu.num_load_insts 419 # Number of load instructions
|
||||
system.cpu.num_mem_refs 717 # number of memory refs
|
||||
system.cpu.num_store_insts 298 # Number of store instructions
|
||||
system.cpu.workload.PROG:num_syscalls 4 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
||||
@@ -1,13 +1,22 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
dummy=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
mem_mode=atomic
|
||||
physmem=system.physmem
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
|
||||
@@ -1,5 +1,3 @@
|
||||
Redirecting stdout to build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing/simout
|
||||
Redirecting stderr to build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing/simerr
|
||||
M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2008
|
||||
@@ -7,11 +5,11 @@ The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Aug 26 2010 11:51:59
|
||||
M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
|
||||
M5 started Aug 26 2010 11:52:05
|
||||
M5 executing on zizzer
|
||||
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing
|
||||
M5 compiled Feb 7 2011 01:47:18
|
||||
M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
|
||||
M5 started Feb 7 2011 01:47:36
|
||||
M5 executing on burrito
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
|
||||
@@ -1,9 +1,9 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 97740 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 203308 # Number of bytes of host memory used
|
||||
host_seconds 0.03 # Real time elapsed on the host
|
||||
host_tick_rate 629585132 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 236465 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 222144 # Number of bytes of host memory used
|
||||
host_seconds 0.01 # Real time elapsed on the host
|
||||
host_tick_rate 1500776387 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 2577 # Number of instructions simulated
|
||||
sim_seconds 0.000017 # Number of seconds simulated
|
||||
@@ -226,8 +226,24 @@ system.cpu.l2cache.warmup_cycle 0 # Cy
|
||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 33538 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.num_busy_cycles 33538 # Number of busy cycles
|
||||
system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls
|
||||
system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses
|
||||
system.cpu.num_fp_insts 6 # number of float instructions
|
||||
system.cpu.num_fp_register_reads 6 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu.num_func_calls 140 # number of times a function call or return occured
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_insts 2577 # Number of instructions executed
|
||||
system.cpu.num_refs 717 # Number of memory references
|
||||
system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses
|
||||
system.cpu.num_int_insts 2375 # number of integer instructions
|
||||
system.cpu.num_int_register_reads 2998 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 1768 # number of times the integer registers were written
|
||||
system.cpu.num_load_insts 419 # Number of load instructions
|
||||
system.cpu.num_mem_refs 717 # number of memory refs
|
||||
system.cpu.num_store_insts 298 # Number of store instructions
|
||||
system.cpu.workload.PROG:num_syscalls 4 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
||||
@@ -1,13 +1,22 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
dummy=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
mem_mode=atomic
|
||||
physmem=system.physmem
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
@@ -484,7 +493,7 @@ egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/chips/pd/randd/dist/test-progs/hello/bin/arm/linux/hello
|
||||
executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
||||
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jan 11 2011 18:16:01
|
||||
M5 revision b39a8457b332 7816 default ext/o3_regressions.patch qtip tip
|
||||
M5 started Jan 12 2011 04:32:17
|
||||
M5 executing on u200439-lin.austin.arm.com
|
||||
M5 compiled Feb 7 2011 01:56:16
|
||||
M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
|
||||
M5 started Feb 7 2011 01:58:16
|
||||
M5 executing on burrito
|
||||
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/quick/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/quick/00.hello/arm/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
@@ -1,9 +1,9 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 59213 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 247916 # Number of bytes of host memory used
|
||||
host_seconds 0.10 # Real time elapsed on the host
|
||||
host_tick_rate 108401013 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 29952 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 234448 # Number of bytes of host memory used
|
||||
host_seconds 0.19 # Real time elapsed on the host
|
||||
host_tick_rate 54904580 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 5620 # Number of instructions simulated
|
||||
sim_seconds 0.000010 # Number of seconds simulated
|
||||
@@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value 0
|
||||
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::total 10656 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:count 5620 # Number of instructions committed
|
||||
system.cpu.commit.COM:fp_insts 16 # Number of committed floating point instructions.
|
||||
system.cpu.commit.COM:function_calls 0 # Number of function calls committed.
|
||||
system.cpu.commit.COM:int_insts 4889 # Number of committed integer instructions.
|
||||
system.cpu.commit.COM:loads 1207 # Number of loads committed
|
||||
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
|
||||
system.cpu.commit.COM:refs 2145 # Number of memory references committed
|
||||
@@ -171,6 +174,7 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 11818 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
|
||||
system.cpu.icache.ReadReq_accesses 1675 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 34635.549872 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 33596.573209 # average ReadReq mshr miss latency
|
||||
@@ -270,6 +274,8 @@ system.cpu.iew.lsq.thread.0.squashedStores 708 #
|
||||
system.cpu.iew.memOrderViolationEvents 34 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 609 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 33 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.int_regfile_reads 19236 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 5710 # number of integer regfile writes
|
||||
system.cpu.ipc 0.272340 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.272340 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
||||
@@ -361,6 +367,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value 0
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::total 11818 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:rate 0.440202 # Inst issue rate
|
||||
system.cpu.iq.fp_alu_accesses 22 # Number of floating point alu accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 54 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_writes 58 # Number of floating instruction queue writes
|
||||
system.cpu.iq.int_alu_accesses 9243 # Number of integer alu accesses
|
||||
system.cpu.iq.int_inst_queue_reads 30172 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 7972 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.int_inst_queue_writes 17831 # Number of integer instruction queue writes
|
||||
system.cpu.iq.iqInstsAdded 11904 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 9084 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 2 # Number of non-speculative instructions added to the IQ
|
||||
@@ -458,7 +472,11 @@ system.cpu.memDep0.conflictingLoads 12 # Nu
|
||||
system.cpu.memDep0.conflictingStores 11 # Number of conflicting stores.
|
||||
system.cpu.memDep0.insertedLoads 2545 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 1646 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.misc_regfile_reads 15396 # number of misc regfile reads
|
||||
system.cpu.misc_regfile_writes 3 # number of misc regfile writes
|
||||
system.cpu.numCycles 20636 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.rename.RENAME:BlockCycles 346 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:CommittedMaps 4006 # Number of HB maps that are committed
|
||||
system.cpu.rename.RENAME:IQFullEvents 46 # Number of times rename has blocked due to IQ full
|
||||
@@ -471,10 +489,14 @@ system.cpu.rename.RENAME:RunCycles 2314 # Nu
|
||||
system.cpu.rename.RENAME:SquashCycles 1162 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 187 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 6085 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:fp_rename_lookups 744 # Number of floating rename lookups
|
||||
system.cpu.rename.RENAME:int_rename_lookups 36764 # Number of integer rename lookups
|
||||
system.cpu.rename.RENAME:serializeStallCycles 271 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 4 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 537 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 1 # count of temporary serializing insts renamed
|
||||
system.cpu.rob.rob_reads 22070 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 24470 # The number of ROB writes
|
||||
system.cpu.timesIdled 180 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.workload.PROG:num_syscalls 13 # Number of system calls
|
||||
|
||||
|
||||
@@ -1,13 +1,22 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
dummy=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
mem_mode=atomic
|
||||
physmem=system.physmem
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
|
||||
[system.cpu]
|
||||
type=AtomicSimpleCPU
|
||||
@@ -57,7 +66,7 @@ egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/chips/pd/randd/dist/test-progs/hello/bin/arm/linux/hello
|
||||
executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
||||
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Oct 11 2010 18:37:23
|
||||
M5 revision c4e3d74d9a68 7726 default ext/mp_boot.patch qtip tip
|
||||
M5 started Oct 11 2010 18:37:39
|
||||
M5 executing on aus-bc3-b4
|
||||
command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/quick/00.hello/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/quick/00.hello/arm/linux/simple-atomic
|
||||
M5 compiled Feb 7 2011 01:56:16
|
||||
M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
|
||||
M5 started Feb 7 2011 01:56:25
|
||||
M5 executing on burrito
|
||||
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/quick/00.hello/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/quick/00.hello/arm/linux/simple-atomic
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Hello world!
|
||||
|
||||
@@ -1,9 +1,9 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 402550 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 249936 # Number of bytes of host memory used
|
||||
host_seconds 0.01 # Real time elapsed on the host
|
||||
host_tick_rate 197047093 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 100802 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 225720 # Number of bytes of host memory used
|
||||
host_seconds 0.06 # Real time elapsed on the host
|
||||
host_tick_rate 50271986 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 5620 # Number of instructions simulated
|
||||
sim_seconds 0.000003 # Number of seconds simulated
|
||||
@@ -53,8 +53,24 @@ system.cpu.itb.write_hits 0 # DT
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 5633 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.num_busy_cycles 5633 # Number of busy cycles
|
||||
system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls
|
||||
system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
|
||||
system.cpu.num_fp_insts 16 # number of float instructions
|
||||
system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu.num_func_calls 0 # number of times a function call or return occured
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_insts 5620 # Number of instructions executed
|
||||
system.cpu.num_refs 2145 # Number of memory references
|
||||
system.cpu.num_int_alu_accesses 4889 # Number of integer alu accesses
|
||||
system.cpu.num_int_insts 4889 # number of integer instructions
|
||||
system.cpu.num_int_register_reads 14091 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 3689 # number of times the integer registers were written
|
||||
system.cpu.num_load_insts 1207 # Number of load instructions
|
||||
system.cpu.num_mem_refs 2145 # number of memory refs
|
||||
system.cpu.num_store_insts 938 # Number of store instructions
|
||||
system.cpu.workload.PROG:num_syscalls 13 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
||||
@@ -1,13 +1,22 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
dummy=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
mem_mode=atomic
|
||||
physmem=system.physmem
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
@@ -157,7 +166,7 @@ egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/chips/pd/randd/dist/test-progs/hello/bin/arm/linux/hello
|
||||
executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
||||
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Dec 7 2010 18:51:32
|
||||
M5 revision 331c8c76d885 7806 default qtip tip ext/mismatched_new_delete.patch
|
||||
M5 started Dec 7 2010 18:51:46
|
||||
M5 executing on u200439-lin.austin.arm.com
|
||||
M5 compiled Feb 7 2011 01:56:16
|
||||
M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
|
||||
M5 started Feb 7 2011 01:58:13
|
||||
M5 executing on burrito
|
||||
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/quick/00.hello/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/quick/00.hello/arm/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
@@ -1,9 +1,9 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 315416 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 248988 # Number of bytes of host memory used
|
||||
host_inst_rate 265936 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 233432 # Number of bytes of host memory used
|
||||
host_seconds 0.02 # Real time elapsed on the host
|
||||
host_tick_rate 1472008046 # Simulator tick rate (ticks/s)
|
||||
host_tick_rate 1242220035 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 5563 # Number of instructions simulated
|
||||
sim_seconds 0.000026 # Number of seconds simulated
|
||||
@@ -237,8 +237,24 @@ system.cpu.l2cache.warmup_cycle 0 # Cy
|
||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 52692 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.num_busy_cycles 52692 # Number of busy cycles
|
||||
system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls
|
||||
system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
|
||||
system.cpu.num_fp_insts 16 # number of float instructions
|
||||
system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu.num_func_calls 0 # number of times a function call or return occured
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_insts 5563 # Number of instructions executed
|
||||
system.cpu.num_refs 2145 # Number of memory references
|
||||
system.cpu.num_int_alu_accesses 4889 # Number of integer alu accesses
|
||||
system.cpu.num_int_insts 4889 # number of integer instructions
|
||||
system.cpu.num_int_register_reads 15212 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 3689 # number of times the integer registers were written
|
||||
system.cpu.num_load_insts 1207 # Number of load instructions
|
||||
system.cpu.num_mem_refs 2145 # number of memory refs
|
||||
system.cpu.num_store_insts 938 # Number of store instructions
|
||||
system.cpu.workload.PROG:num_syscalls 13 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
||||
@@ -1,13 +1,22 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
dummy=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
mem_mode=atomic
|
||||
physmem=system.physmem
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
|
||||
[system.cpu]
|
||||
type=InOrderCPU
|
||||
@@ -246,7 +255,7 @@ egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=tests/test-progs/hello/bin/mips/linux/hello
|
||||
executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
||||
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jan 24 2011 18:37:16
|
||||
M5 revision 09e8ac96522d+ 7823+ default regression_updates qtip tip
|
||||
M5 started Jan 24 2011 18:37:18
|
||||
M5 executing on zooks
|
||||
M5 compiled Feb 7 2011 01:55:51
|
||||
M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
|
||||
M5 started Feb 7 2011 01:56:02
|
||||
M5 executing on burrito
|
||||
command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/inorder-timing -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/inorder-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
@@ -1,9 +1,9 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 32637 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 156860 # Number of bytes of host memory used
|
||||
host_inst_rate 32668 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 224608 # Number of bytes of host memory used
|
||||
host_seconds 0.18 # Real time elapsed on the host
|
||||
host_tick_rate 120410651 # Simulator tick rate (ticks/s)
|
||||
host_tick_rate 120542676 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 5827 # Number of instructions simulated
|
||||
sim_seconds 0.000022 # Number of seconds simulated
|
||||
@@ -253,6 +253,8 @@ system.cpu.l2cache.total_refs 2 # To
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||
system.cpu.numCycles 43069 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.runCycles 6002 # Number of cycles cpu stages are processed.
|
||||
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread)
|
||||
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
|
||||
|
||||
@@ -1,13 +1,22 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
dummy=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
mem_mode=atomic
|
||||
physmem=system.physmem
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
|
||||
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jan 17 2011 21:17:36
|
||||
M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase
|
||||
M5 started Jan 17 2011 21:17:39
|
||||
M5 executing on zizzer
|
||||
M5 compiled Feb 7 2011 01:55:51
|
||||
M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
|
||||
M5 started Feb 7 2011 01:56:01
|
||||
M5 executing on burrito
|
||||
command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
@@ -1,9 +1,9 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 35741 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 204488 # Number of bytes of host memory used
|
||||
host_inst_rate 37179 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 224748 # Number of bytes of host memory used
|
||||
host_seconds 0.14 # Real time elapsed on the host
|
||||
host_tick_rate 88262097 # Simulator tick rate (ticks/s)
|
||||
host_tick_rate 91756799 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 5169 # Number of instructions simulated
|
||||
sim_seconds 0.000013 # Number of seconds simulated
|
||||
@@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value 0
|
||||
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::total 12273 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:count 5826 # Number of instructions committed
|
||||
system.cpu.commit.COM:fp_insts 2 # Number of committed floating point instructions.
|
||||
system.cpu.commit.COM:function_calls 87 # Number of function calls committed.
|
||||
system.cpu.commit.COM:int_insts 5124 # Number of committed integer instructions.
|
||||
system.cpu.commit.COM:loads 1164 # Number of loads committed
|
||||
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
|
||||
system.cpu.commit.COM:refs 2089 # Number of memory references committed
|
||||
@@ -162,6 +165,8 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 12922 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fp_regfile_reads 3 # number of floating regfile reads
|
||||
system.cpu.fp_regfile_writes 1 # number of floating regfile writes
|
||||
system.cpu.icache.ReadReq_accesses 1555 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 36274.074074 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35024.316109 # average ReadReq mshr miss latency
|
||||
@@ -261,6 +266,8 @@ system.cpu.iew.lsq.thread.0.squashedStores 210 #
|
||||
system.cpu.iew.memOrderViolationEvents 16 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 259 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 118 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.int_regfile_reads 9780 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 4751 # number of integer regfile writes
|
||||
system.cpu.ipc 0.202151 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.202151 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
||||
@@ -352,6 +359,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value 0
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::total 12922 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:rate 0.288346 # Inst issue rate
|
||||
system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes
|
||||
system.cpu.iq.int_alu_accesses 7513 # Number of integer alu accesses
|
||||
system.cpu.iq.int_inst_queue_reads 27837 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 6791 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.int_inst_queue_writes 10538 # Number of integer instruction queue writes
|
||||
system.cpu.iq.iqInstsAdded 8058 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 7373 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 11 # Number of non-speculative instructions added to the IQ
|
||||
@@ -436,7 +451,10 @@ system.cpu.memDep0.conflictingLoads 5 # Nu
|
||||
system.cpu.memDep0.conflictingStores 1 # Number of conflicting stores.
|
||||
system.cpu.memDep0.insertedLoads 2139 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 1135 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.misc_regfile_reads 136 # number of misc regfile reads
|
||||
system.cpu.numCycles 25570 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.rename.RENAME:BlockCycles 238 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:CommittedMaps 3410 # Number of HB maps that are committed
|
||||
system.cpu.rename.RENAME:IdleCycles 8931 # Number of cycles rename is idle
|
||||
@@ -448,10 +466,14 @@ system.cpu.rename.RENAME:RunCycles 2609 # Nu
|
||||
system.cpu.rename.RENAME:SquashCycles 649 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 81 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 2709 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:fp_rename_lookups 5 # Number of floating rename lookups
|
||||
system.cpu.rename.RENAME:int_rename_lookups 12083 # Number of integer rename lookups
|
||||
system.cpu.rename.RENAME:serializeStallCycles 414 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 16 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 196 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 11 # count of temporary serializing insts renamed
|
||||
system.cpu.rob.rob_reads 21491 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 19268 # The number of ROB writes
|
||||
system.cpu.timesIdled 259 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.workload.PROG:num_syscalls 8 # Number of system calls
|
||||
|
||||
|
||||
@@ -1,13 +1,22 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
dummy=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
mem_mode=atomic
|
||||
physmem=system.physmem
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
|
||||
[system.cpu]
|
||||
type=AtomicSimpleCPU
|
||||
@@ -111,7 +120,7 @@ egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/mips/linux/hello
|
||||
executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
||||
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Feb 24 2010 23:13:04
|
||||
M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
|
||||
M5 started Feb 25 2010 03:11:22
|
||||
M5 executing on SC2B0619
|
||||
M5 compiled Feb 7 2011 01:55:51
|
||||
M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
|
||||
M5 started Feb 7 2011 01:56:01
|
||||
M5 executing on burrito
|
||||
command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
@@ -1,9 +1,9 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 1101929 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 183300 # Number of bytes of host memory used
|
||||
host_seconds 0.01 # Real time elapsed on the host
|
||||
host_tick_rate 525428314 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 106820 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 216064 # Number of bytes of host memory used
|
||||
host_seconds 0.05 # Real time elapsed on the host
|
||||
host_tick_rate 53148750 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 5827 # Number of instructions simulated
|
||||
sim_seconds 0.000003 # Number of seconds simulated
|
||||
@@ -29,8 +29,24 @@ system.cpu.itb.write_hits 0 # DT
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 5828 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.num_busy_cycles 5828 # Number of busy cycles
|
||||
system.cpu.num_conditional_control_insts 677 # number of instructions that are conditional controls
|
||||
system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses
|
||||
system.cpu.num_fp_insts 2 # number of float instructions
|
||||
system.cpu.num_fp_register_reads 3 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 1 # number of times the floating registers were written
|
||||
system.cpu.num_func_calls 194 # number of times a function call or return occured
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_insts 5827 # Number of instructions executed
|
||||
system.cpu.num_refs 2090 # Number of memory references
|
||||
system.cpu.num_int_alu_accesses 5126 # Number of integer alu accesses
|
||||
system.cpu.num_int_insts 5126 # number of integer instructions
|
||||
system.cpu.num_int_register_reads 7301 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 3409 # number of times the integer registers were written
|
||||
system.cpu.num_load_insts 1164 # Number of load instructions
|
||||
system.cpu.num_mem_refs 2090 # number of memory refs
|
||||
system.cpu.num_store_insts 926 # Number of store instructions
|
||||
system.cpu.workload.PROG:num_syscalls 8 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
||||
@@ -1,13 +1,22 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
dummy=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000
|
||||
time_sync_spin_threshold=100000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu physmem ruby
|
||||
mem_mode=atomic
|
||||
children=cpu dir_cntrl0 l1_cntrl0 physmem ruby
|
||||
mem_mode=timing
|
||||
physmem=system.physmem
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
@@ -86,8 +95,8 @@ progress_interval=0
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[1]
|
||||
icache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0]
|
||||
dcache_port=system.ruby.cpu_ruby_ports.port[1]
|
||||
icache_port=system.ruby.cpu_ruby_ports.port[0]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=MipsTLB
|
||||
@@ -108,7 +117,7 @@ egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=tests/test-progs/hello/bin/mips/linux/hello
|
||||
executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
@@ -119,127 +128,27 @@ simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
latency=30
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort
|
||||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
children=debug network profiler tracer
|
||||
block_size_bytes=64
|
||||
clock=1
|
||||
debug=system.ruby.debug
|
||||
mem_size=134217728
|
||||
network=system.ruby.network
|
||||
profiler=system.ruby.profiler
|
||||
random_seed=1234
|
||||
randomization=false
|
||||
stats_filename=ruby.stats
|
||||
tech_nm=45
|
||||
tracer=system.ruby.tracer
|
||||
|
||||
[system.ruby.debug]
|
||||
type=RubyDebug
|
||||
filter_string=none
|
||||
output_filename=none
|
||||
protocol_trace=false
|
||||
start_time=1
|
||||
verbosity_string=none
|
||||
|
||||
[system.ruby.network]
|
||||
type=SimpleNetwork
|
||||
children=topology
|
||||
adaptive_routing=true
|
||||
buffer_size=0
|
||||
control_msg_size=8
|
||||
endpoint_bandwidth=10000
|
||||
link_latency=1
|
||||
number_of_virtual_networks=10
|
||||
topology=system.ruby.network.topology
|
||||
|
||||
[system.ruby.network.topology]
|
||||
type=Topology
|
||||
children=ext_links0 ext_links1 int_links0 int_links1
|
||||
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1
|
||||
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1
|
||||
num_int_nodes=3
|
||||
print_config=false
|
||||
|
||||
[system.ruby.network.topology.ext_links0]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links0.ext_node
|
||||
int_node=0
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=sequencer
|
||||
buffer_size=0
|
||||
cacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
cache_response_latency=12
|
||||
issue_latency=2
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.sequencer]
|
||||
type=RubySequencer
|
||||
children=icache
|
||||
dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
physMemPort=system.physmem.port[0]
|
||||
port=system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links1]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links1.ext_node
|
||||
int_node=1
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node]
|
||||
[system.dir_cntrl0]
|
||||
type=Directory_Controller
|
||||
children=directory memBuffer
|
||||
buffer_size=0
|
||||
directory=system.ruby.network.topology.ext_links1.ext_node.directory
|
||||
directory=system.dir_cntrl0.directory
|
||||
directory_latency=12
|
||||
memBuffer=system.ruby.network.topology.ext_links1.ext_node.memBuffer
|
||||
memBuffer=system.dir_cntrl0.memBuffer
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node.directory]
|
||||
[system.dir_cntrl0.directory]
|
||||
type=RubyDirectoryMemory
|
||||
map_levels=4
|
||||
numa_high_bit=6
|
||||
size=134217728
|
||||
use_map=false
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node.memBuffer]
|
||||
[system.dir_cntrl0.memBuffer]
|
||||
type=RubyMemoryControl
|
||||
bank_bit_0=8
|
||||
bank_busy_time=11
|
||||
@@ -260,6 +169,100 @@ refresh_period=1560
|
||||
tFaw=0
|
||||
version=0
|
||||
|
||||
[system.l1_cntrl0]
|
||||
type=L1Cache_Controller
|
||||
buffer_size=0
|
||||
cacheMemory=system.ruby.cpu_ruby_ports.dcache
|
||||
cache_response_latency=12
|
||||
issue_latency=2
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.ruby.cpu_ruby_ports
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
latency=30
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.ruby.cpu_ruby_ports.physMemPort
|
||||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
children=cpu_ruby_ports network profiler tracer
|
||||
block_size_bytes=64
|
||||
clock=1
|
||||
mem_size=134217728
|
||||
network=system.ruby.network
|
||||
no_mem_vec=false
|
||||
profiler=system.ruby.profiler
|
||||
random_seed=1234
|
||||
randomization=false
|
||||
stats_filename=ruby.stats
|
||||
tracer=system.ruby.tracer
|
||||
|
||||
[system.ruby.cpu_ruby_ports]
|
||||
type=RubySequencer
|
||||
children=dcache
|
||||
access_phys_mem=true
|
||||
dcache=system.ruby.cpu_ruby_ports.dcache
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.cpu_ruby_ports.dcache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
physMemPort=system.physmem.port[0]
|
||||
port=system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
[system.ruby.cpu_ruby_ports.dcache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.ruby.network]
|
||||
type=SimpleNetwork
|
||||
children=topology
|
||||
adaptive_routing=false
|
||||
buffer_size=0
|
||||
control_msg_size=8
|
||||
endpoint_bandwidth=10000
|
||||
link_latency=1
|
||||
number_of_virtual_networks=10
|
||||
topology=system.ruby.network.topology
|
||||
|
||||
[system.ruby.network.topology]
|
||||
type=Topology
|
||||
children=ext_links0 ext_links1 int_links0 int_links1
|
||||
description=Crossbar
|
||||
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1
|
||||
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1
|
||||
num_int_nodes=3
|
||||
print_config=false
|
||||
|
||||
[system.ruby.network.topology.ext_links0]
|
||||
type=ExtLink
|
||||
bw_multiplier=64
|
||||
ext_node=system.l1_cntrl0
|
||||
int_node=0
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links1]
|
||||
type=ExtLink
|
||||
bw_multiplier=64
|
||||
ext_node=system.dir_cntrl0
|
||||
int_node=1
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.int_links0]
|
||||
type=IntLink
|
||||
bw_multiplier=16
|
||||
|
||||
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jan 21 2010 11:12:15
|
||||
M5 revision a2fac757fb31+ 6860+ default qtip brad/rubycfg_orion_update tip
|
||||
M5 started Jan 21 2010 11:12:51
|
||||
M5 executing on svvint07
|
||||
M5 compiled Feb 7 2011 01:55:51
|
||||
M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
|
||||
M5 started Feb 7 2011 01:56:00
|
||||
M5 executing on burrito
|
||||
command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing-ruby -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing-ruby
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
@@ -1,9 +1,9 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 24278 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 347460 # Number of bytes of host memory used
|
||||
host_inst_rate 24226 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 234168 # Number of bytes of host memory used
|
||||
host_seconds 0.24 # Real time elapsed on the host
|
||||
host_tick_rate 1220626 # Simulator tick rate (ticks/s)
|
||||
host_tick_rate 1216878 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
sim_insts 5827 # Number of instructions simulated
|
||||
sim_seconds 0.000293 # Number of seconds simulated
|
||||
@@ -29,8 +29,24 @@ system.cpu.itb.write_hits 0 # DT
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 292960 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.num_busy_cycles 292960 # Number of busy cycles
|
||||
system.cpu.num_conditional_control_insts 677 # number of instructions that are conditional controls
|
||||
system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses
|
||||
system.cpu.num_fp_insts 2 # number of float instructions
|
||||
system.cpu.num_fp_register_reads 3 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 1 # number of times the floating registers were written
|
||||
system.cpu.num_func_calls 194 # number of times a function call or return occured
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_insts 5827 # Number of instructions executed
|
||||
system.cpu.num_refs 2090 # Number of memory references
|
||||
system.cpu.num_int_alu_accesses 5126 # Number of integer alu accesses
|
||||
system.cpu.num_int_insts 5126 # number of integer instructions
|
||||
system.cpu.num_int_register_reads 7301 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 3409 # number of times the integer registers were written
|
||||
system.cpu.num_load_insts 1164 # Number of load instructions
|
||||
system.cpu.num_mem_refs 2090 # number of memory refs
|
||||
system.cpu.num_store_insts 926 # Number of store instructions
|
||||
system.cpu.workload.PROG:num_syscalls 8 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
||||
@@ -1,13 +1,22 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
dummy=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
mem_mode=atomic
|
||||
physmem=system.physmem
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
|
||||
@@ -1,5 +1,3 @@
|
||||
Redirecting stdout to build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing/simout
|
||||
Redirecting stderr to build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing/simerr
|
||||
M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2008
|
||||
@@ -7,11 +5,11 @@ The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Aug 26 2010 12:56:28
|
||||
M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
|
||||
M5 started Aug 26 2010 12:56:30
|
||||
M5 executing on zizzer
|
||||
command line: build/MIPS_SE/m5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing
|
||||
M5 compiled Feb 7 2011 01:55:51
|
||||
M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
|
||||
M5 started Feb 7 2011 01:56:00
|
||||
M5 executing on burrito
|
||||
command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
|
||||
@@ -1,9 +1,9 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 5098 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 204896 # Number of bytes of host memory used
|
||||
host_seconds 1.14 # Real time elapsed on the host
|
||||
host_tick_rate 28066026 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 344481 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 223780 # Number of bytes of host memory used
|
||||
host_seconds 0.02 # Real time elapsed on the host
|
||||
host_tick_rate 1868884758 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 5827 # Number of instructions simulated
|
||||
sim_seconds 0.000032 # Number of seconds simulated
|
||||
@@ -213,8 +213,24 @@ system.cpu.l2cache.warmup_cycle 0 # Cy
|
||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 64176 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.num_busy_cycles 64176 # Number of busy cycles
|
||||
system.cpu.num_conditional_control_insts 677 # number of instructions that are conditional controls
|
||||
system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses
|
||||
system.cpu.num_fp_insts 2 # number of float instructions
|
||||
system.cpu.num_fp_register_reads 3 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 1 # number of times the floating registers were written
|
||||
system.cpu.num_func_calls 194 # number of times a function call or return occured
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_insts 5827 # Number of instructions executed
|
||||
system.cpu.num_refs 2090 # Number of memory references
|
||||
system.cpu.num_int_alu_accesses 5126 # Number of integer alu accesses
|
||||
system.cpu.num_int_insts 5126 # number of integer instructions
|
||||
system.cpu.num_int_register_reads 7301 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 3409 # number of times the integer registers were written
|
||||
system.cpu.num_load_insts 1164 # Number of load instructions
|
||||
system.cpu.num_mem_refs 2090 # number of memory refs
|
||||
system.cpu.num_store_insts 926 # Number of store instructions
|
||||
system.cpu.workload.PROG:num_syscalls 8 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
||||
@@ -1,13 +1,22 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
dummy=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
mem_mode=atomic
|
||||
physmem=system.physmem
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
For more information see: http://www.m5sim.org/warn/d946bea6
|
||||
warn: allowing mmap of file @ fd 16206088. This will break if not /dev/zero.
|
||||
warn: allowing mmap of file @ fd 42898616. This will break if not /dev/zero.
|
||||
For more information see: http://www.m5sim.org/warn/3a2134f6
|
||||
hack: be nice to actually delete the event here
|
||||
|
||||
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jan 17 2011 17:18:01
|
||||
M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase
|
||||
M5 started Jan 17 2011 17:18:03
|
||||
M5 executing on zizzer
|
||||
M5 compiled Feb 7 2011 02:06:34
|
||||
M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
|
||||
M5 started Feb 7 2011 02:06:41
|
||||
M5 executing on burrito
|
||||
command line: build/POWER_SE/m5.fast -d build/POWER_SE/tests/fast/quick/00.hello/power/linux/o3-timing -re tests/run.py build/POWER_SE/tests/fast/quick/00.hello/power/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
@@ -1,9 +1,9 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 12762 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 202140 # Number of bytes of host memory used
|
||||
host_seconds 0.45 # Real time elapsed on the host
|
||||
host_tick_rate 25804848 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 32835 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 222408 # Number of bytes of host memory used
|
||||
host_seconds 0.18 # Real time elapsed on the host
|
||||
host_tick_rate 66311402 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 5800 # Number of instructions simulated
|
||||
sim_seconds 0.000012 # Number of seconds simulated
|
||||
@@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value 0
|
||||
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::total 10473 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:count 5800 # Number of instructions committed
|
||||
system.cpu.commit.COM:fp_insts 22 # Number of committed floating point instructions.
|
||||
system.cpu.commit.COM:function_calls 103 # Number of function calls committed.
|
||||
system.cpu.commit.COM:int_insts 5706 # Number of committed integer instructions.
|
||||
system.cpu.commit.COM:loads 962 # Number of loads committed
|
||||
system.cpu.commit.COM:membars 7 # Number of memory barriers committed
|
||||
system.cpu.commit.COM:refs 2008 # Number of memory references committed
|
||||
@@ -162,6 +165,8 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 11043 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fp_regfile_reads 25 # number of floating regfile reads
|
||||
system.cpu.fp_regfile_writes 2 # number of floating regfile writes
|
||||
system.cpu.icache.ReadReq_accesses 1490 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 36422.279793 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 34777.108434 # average ReadReq mshr miss latency
|
||||
@@ -261,6 +266,8 @@ system.cpu.iew.lsq.thread.0.squashedStores 404 #
|
||||
system.cpu.iew.memOrderViolationEvents 42 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 201 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 76 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.int_regfile_reads 12419 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 6594 # number of integer regfile writes
|
||||
system.cpu.ipc 0.247156 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.247156 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
||||
@@ -352,6 +359,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value 0
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::total 11043 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:rate 0.344697 # Inst issue rate
|
||||
system.cpu.iq.fp_alu_accesses 31 # Number of floating point alu accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 59 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_writes 36 # Number of floating instruction queue writes
|
||||
system.cpu.iq.int_alu_accesses 8211 # Number of integer alu accesses
|
||||
system.cpu.iq.int_inst_queue_reads 27329 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 7555 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.int_inst_queue_writes 12158 # Number of integer instruction queue writes
|
||||
system.cpu.iq.iqInstsAdded 9163 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 8089 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 22 # Number of non-speculative instructions added to the IQ
|
||||
@@ -437,6 +452,8 @@ system.cpu.memDep0.conflictingStores 29 # Nu
|
||||
system.cpu.memDep0.insertedLoads 1681 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 1450 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.numCycles 23467 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.rename.RENAME:BlockCycles 312 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:CommittedMaps 5007 # Number of HB maps that are committed
|
||||
system.cpu.rename.RENAME:IQFullEvents 7 # Number of times rename has blocked due to IQ full
|
||||
@@ -449,10 +466,14 @@ system.cpu.rename.RENAME:RunCycles 1825 # Nu
|
||||
system.cpu.rename.RENAME:SquashCycles 570 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 243 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 3701 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:fp_rename_lookups 55 # Number of floating rename lookups
|
||||
system.cpu.rename.RENAME:int_rename_lookups 16177 # Number of integer rename lookups
|
||||
system.cpu.rename.RENAME:serializeStallCycles 337 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 22 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 473 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 22 # count of temporary serializing insts renamed
|
||||
system.cpu.rob.rob_reads 19611 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 18950 # The number of ROB writes
|
||||
system.cpu.timesIdled 230 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.workload.PROG:num_syscalls 9 # Number of system calls
|
||||
|
||||
|
||||
@@ -1,13 +1,22 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
dummy=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
mem_mode=atomic
|
||||
physmem=system.physmem
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
|
||||
[system.cpu]
|
||||
type=AtomicSimpleCPU
|
||||
@@ -58,7 +67,7 @@ egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/power/linux/hello
|
||||
executable=/dist/m5/regression/test-progs/hello/bin/power/linux/hello
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
For more information see: http://www.m5sim.org/warn/d946bea6
|
||||
warn: allowing mmap of file @ fd 13074680. This will break if not /dev/zero.
|
||||
warn: allowing mmap of file @ fd 39589752. This will break if not /dev/zero.
|
||||
For more information see: http://www.m5sim.org/warn/3a2134f6
|
||||
hack: be nice to actually delete the event here
|
||||
|
||||
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Feb 24 2010 23:13:07
|
||||
M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
|
||||
M5 started Feb 24 2010 23:13:11
|
||||
M5 executing on SC2B0619
|
||||
M5 compiled Feb 7 2011 02:06:34
|
||||
M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
|
||||
M5 started Feb 7 2011 02:06:40
|
||||
M5 executing on burrito
|
||||
command line: build/POWER_SE/m5.fast -d build/POWER_SE/tests/fast/quick/00.hello/power/linux/simple-atomic -re tests/run.py build/POWER_SE/tests/fast/quick/00.hello/power/linux/simple-atomic
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
@@ -1,9 +1,9 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 277162 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 181156 # Number of bytes of host memory used
|
||||
host_seconds 0.02 # Real time elapsed on the host
|
||||
host_tick_rate 136566988 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 628022 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 214048 # Number of bytes of host memory used
|
||||
host_seconds 0.01 # Real time elapsed on the host
|
||||
host_tick_rate 304927994 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 5801 # Number of instructions simulated
|
||||
sim_seconds 0.000003 # Number of seconds simulated
|
||||
@@ -29,8 +29,24 @@ system.cpu.itb.write_hits 0 # DT
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 5801 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.num_busy_cycles 5801 # Number of busy cycles
|
||||
system.cpu.num_conditional_control_insts 896 # number of instructions that are conditional controls
|
||||
system.cpu.num_fp_alu_accesses 22 # Number of float alu accesses
|
||||
system.cpu.num_fp_insts 22 # number of float instructions
|
||||
system.cpu.num_fp_register_reads 20 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
|
||||
system.cpu.num_func_calls 200 # number of times a function call or return occured
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_insts 5801 # Number of instructions executed
|
||||
system.cpu.num_refs 2008 # Number of memory references
|
||||
system.cpu.num_int_alu_accesses 5706 # Number of integer alu accesses
|
||||
system.cpu.num_int_insts 5706 # number of integer instructions
|
||||
system.cpu.num_int_register_reads 9541 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 5005 # number of times the integer registers were written
|
||||
system.cpu.num_load_insts 962 # Number of load instructions
|
||||
system.cpu.num_mem_refs 2008 # number of memory refs
|
||||
system.cpu.num_store_insts 1046 # Number of store instructions
|
||||
system.cpu.workload.PROG:num_syscalls 9 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
||||
@@ -1,13 +1,22 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
dummy=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
mem_mode=atomic
|
||||
physmem=system.physmem
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
|
||||
[system.cpu]
|
||||
type=AtomicSimpleCPU
|
||||
@@ -57,7 +66,7 @@ egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/sparc/linux/hello
|
||||
executable=/dist/m5/regression/test-progs/hello/bin/sparc/linux/hello
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
||||
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Feb 25 2010 03:11:27
|
||||
M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
|
||||
M5 started Feb 25 2010 03:37:59
|
||||
M5 executing on SC2B0619
|
||||
M5 compiled Feb 7 2011 02:13:30
|
||||
M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
|
||||
M5 started Feb 7 2011 02:14:08
|
||||
M5 executing on burrito
|
||||
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-atomic
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
@@ -1,9 +1,9 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 897027 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 182692 # Number of bytes of host memory used
|
||||
host_seconds 0.01 # Real time elapsed on the host
|
||||
host_tick_rate 434663663 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 96674 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 215848 # Number of bytes of host memory used
|
||||
host_seconds 0.06 # Real time elapsed on the host
|
||||
host_tick_rate 48656953 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 5340 # Number of instructions simulated
|
||||
sim_seconds 0.000003 # Number of seconds simulated
|
||||
@@ -11,8 +11,24 @@ sim_ticks 2701000 # Nu
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 5403 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.num_busy_cycles 5403 # Number of busy cycles
|
||||
system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls
|
||||
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
|
||||
system.cpu.num_fp_insts 0 # number of float instructions
|
||||
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu.num_func_calls 0 # number of times a function call or return occured
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_insts 5340 # Number of instructions executed
|
||||
system.cpu.num_refs 1402 # Number of memory references
|
||||
system.cpu.num_int_alu_accesses 4517 # Number of integer alu accesses
|
||||
system.cpu.num_int_insts 4517 # number of integer instructions
|
||||
system.cpu.num_int_register_reads 10620 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 4859 # number of times the integer registers were written
|
||||
system.cpu.num_load_insts 724 # Number of load instructions
|
||||
system.cpu.num_mem_refs 1402 # number of memory refs
|
||||
system.cpu.num_store_insts 678 # Number of store instructions
|
||||
system.cpu.workload.PROG:num_syscalls 11 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
||||
@@ -1,13 +1,22 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
dummy=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000
|
||||
time_sync_spin_threshold=100000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu physmem ruby
|
||||
mem_mode=atomic
|
||||
children=cpu dir_cntrl0 l1_cntrl0 physmem ruby
|
||||
mem_mode=timing
|
||||
physmem=system.physmem
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
@@ -32,8 +41,8 @@ progress_interval=0
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[1]
|
||||
icache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0]
|
||||
dcache_port=system.ruby.cpu_ruby_ports.port[1]
|
||||
icache_port=system.ruby.cpu_ruby_ports.port[0]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=SparcTLB
|
||||
@@ -54,7 +63,7 @@ egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=tests/test-progs/hello/bin/sparc/linux/hello
|
||||
executable=/dist/m5/regression/test-progs/hello/bin/sparc/linux/hello
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
@@ -65,127 +74,27 @@ simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
latency=30
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort
|
||||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
children=debug network profiler tracer
|
||||
block_size_bytes=64
|
||||
clock=1
|
||||
debug=system.ruby.debug
|
||||
mem_size=134217728
|
||||
network=system.ruby.network
|
||||
profiler=system.ruby.profiler
|
||||
random_seed=1234
|
||||
randomization=false
|
||||
stats_filename=ruby.stats
|
||||
tech_nm=45
|
||||
tracer=system.ruby.tracer
|
||||
|
||||
[system.ruby.debug]
|
||||
type=RubyDebug
|
||||
filter_string=none
|
||||
output_filename=none
|
||||
protocol_trace=false
|
||||
start_time=1
|
||||
verbosity_string=none
|
||||
|
||||
[system.ruby.network]
|
||||
type=SimpleNetwork
|
||||
children=topology
|
||||
adaptive_routing=true
|
||||
buffer_size=0
|
||||
control_msg_size=8
|
||||
endpoint_bandwidth=10000
|
||||
link_latency=1
|
||||
number_of_virtual_networks=10
|
||||
topology=system.ruby.network.topology
|
||||
|
||||
[system.ruby.network.topology]
|
||||
type=Topology
|
||||
children=ext_links0 ext_links1 int_links0 int_links1
|
||||
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1
|
||||
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1
|
||||
num_int_nodes=3
|
||||
print_config=false
|
||||
|
||||
[system.ruby.network.topology.ext_links0]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links0.ext_node
|
||||
int_node=0
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=sequencer
|
||||
buffer_size=0
|
||||
cacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
cache_response_latency=12
|
||||
issue_latency=2
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.sequencer]
|
||||
type=RubySequencer
|
||||
children=icache
|
||||
dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
physMemPort=system.physmem.port[0]
|
||||
port=system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links1]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links1.ext_node
|
||||
int_node=1
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node]
|
||||
[system.dir_cntrl0]
|
||||
type=Directory_Controller
|
||||
children=directory memBuffer
|
||||
buffer_size=0
|
||||
directory=system.ruby.network.topology.ext_links1.ext_node.directory
|
||||
directory=system.dir_cntrl0.directory
|
||||
directory_latency=12
|
||||
memBuffer=system.ruby.network.topology.ext_links1.ext_node.memBuffer
|
||||
memBuffer=system.dir_cntrl0.memBuffer
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node.directory]
|
||||
[system.dir_cntrl0.directory]
|
||||
type=RubyDirectoryMemory
|
||||
map_levels=4
|
||||
numa_high_bit=6
|
||||
size=134217728
|
||||
use_map=false
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node.memBuffer]
|
||||
[system.dir_cntrl0.memBuffer]
|
||||
type=RubyMemoryControl
|
||||
bank_bit_0=8
|
||||
bank_busy_time=11
|
||||
@@ -206,6 +115,100 @@ refresh_period=1560
|
||||
tFaw=0
|
||||
version=0
|
||||
|
||||
[system.l1_cntrl0]
|
||||
type=L1Cache_Controller
|
||||
buffer_size=0
|
||||
cacheMemory=system.ruby.cpu_ruby_ports.dcache
|
||||
cache_response_latency=12
|
||||
issue_latency=2
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.ruby.cpu_ruby_ports
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
latency=30
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.ruby.cpu_ruby_ports.physMemPort
|
||||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
children=cpu_ruby_ports network profiler tracer
|
||||
block_size_bytes=64
|
||||
clock=1
|
||||
mem_size=134217728
|
||||
network=system.ruby.network
|
||||
no_mem_vec=false
|
||||
profiler=system.ruby.profiler
|
||||
random_seed=1234
|
||||
randomization=false
|
||||
stats_filename=ruby.stats
|
||||
tracer=system.ruby.tracer
|
||||
|
||||
[system.ruby.cpu_ruby_ports]
|
||||
type=RubySequencer
|
||||
children=dcache
|
||||
access_phys_mem=true
|
||||
dcache=system.ruby.cpu_ruby_ports.dcache
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.cpu_ruby_ports.dcache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
physMemPort=system.physmem.port[0]
|
||||
port=system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
[system.ruby.cpu_ruby_ports.dcache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.ruby.network]
|
||||
type=SimpleNetwork
|
||||
children=topology
|
||||
adaptive_routing=false
|
||||
buffer_size=0
|
||||
control_msg_size=8
|
||||
endpoint_bandwidth=10000
|
||||
link_latency=1
|
||||
number_of_virtual_networks=10
|
||||
topology=system.ruby.network.topology
|
||||
|
||||
[system.ruby.network.topology]
|
||||
type=Topology
|
||||
children=ext_links0 ext_links1 int_links0 int_links1
|
||||
description=Crossbar
|
||||
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1
|
||||
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1
|
||||
num_int_nodes=3
|
||||
print_config=false
|
||||
|
||||
[system.ruby.network.topology.ext_links0]
|
||||
type=ExtLink
|
||||
bw_multiplier=64
|
||||
ext_node=system.l1_cntrl0
|
||||
int_node=0
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links1]
|
||||
type=ExtLink
|
||||
bw_multiplier=64
|
||||
ext_node=system.dir_cntrl0
|
||||
int_node=1
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.int_links0]
|
||||
type=IntLink
|
||||
bw_multiplier=16
|
||||
|
||||
@@ -4,16 +4,11 @@
|
||||
RubySystem config:
|
||||
random_seed: 1234
|
||||
randomization: 0
|
||||
tech_nm: 45
|
||||
cycle_period: 1
|
||||
block_size_bytes: 64
|
||||
block_size_bits: 6
|
||||
memory_size_bytes: 134217728
|
||||
memory_size_bits: 27
|
||||
DirectoryMemory Global Config:
|
||||
number of directory memories: 1
|
||||
total memory size bytes: 134217728
|
||||
total memory size bits: 27
|
||||
|
||||
Network Configuration
|
||||
---------------------
|
||||
@@ -23,9 +18,9 @@ topology:
|
||||
virtual_net_0: active, ordered
|
||||
virtual_net_1: active, ordered
|
||||
virtual_net_2: active, ordered
|
||||
virtual_net_3: inactive
|
||||
virtual_net_3: active, ordered
|
||||
virtual_net_4: active, ordered
|
||||
virtual_net_5: active, ordered
|
||||
virtual_net_5: inactive
|
||||
virtual_net_6: inactive
|
||||
virtual_net_7: inactive
|
||||
virtual_net_8: inactive
|
||||
@@ -39,7 +34,7 @@ periodic_stats_period: 1000000
|
||||
================ End RubySystem Configuration Print ================
|
||||
|
||||
|
||||
Real time: Jan/21/2010 11:30:49
|
||||
Real time: Feb/07/2011 02:13:39
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
@@ -48,31 +43,20 @@ Elapsed_time_in_minutes: 0.0166667
|
||||
Elapsed_time_in_hours: 0.000277778
|
||||
Elapsed_time_in_days: 1.15741e-05
|
||||
|
||||
Virtual_time_in_seconds: 0.28
|
||||
Virtual_time_in_minutes: 0.00466667
|
||||
Virtual_time_in_hours: 7.77778e-05
|
||||
Virtual_time_in_days: 3.24074e-06
|
||||
Virtual_time_in_seconds: 0.34
|
||||
Virtual_time_in_minutes: 0.00566667
|
||||
Virtual_time_in_hours: 9.44444e-05
|
||||
Virtual_time_in_days: 3.93519e-06
|
||||
|
||||
Ruby_current_time: 253364
|
||||
Ruby_start_time: 0
|
||||
Ruby_cycles: 253364
|
||||
|
||||
mbytes_resident: 34.3555
|
||||
mbytes_total: 34.5312
|
||||
resident_ratio: 0.995136
|
||||
|
||||
Total_misses: 0
|
||||
total_misses: 0 [ 0 ]
|
||||
user_misses: 0 [ 0 ]
|
||||
supervisor_misses: 0 [ 0 ]
|
||||
|
||||
ruby_cycles_executed: 253365 [ 253365 ]
|
||||
|
||||
transactions_started: 0 [ 0 ]
|
||||
transactions_ended: 0 [ 0 ]
|
||||
cycles_per_transaction: 0 [ 0 ]
|
||||
misses_per_transaction: 0 [ 0 ]
|
||||
mbytes_resident: 37.8555
|
||||
mbytes_total: 228.355
|
||||
resident_ratio: 0.165791
|
||||
|
||||
ruby_cycles_executed: [ 253365 ]
|
||||
|
||||
Busy Controller Counts:
|
||||
L1Cache-0:0
|
||||
@@ -86,9 +70,27 @@ sequencer_requests_outstanding: [binsize: 1 max: 1 count: 6773 average: 1 |
|
||||
All Non-Zero Cycle Demand Cache Accesses
|
||||
----------------------------------------
|
||||
miss_latency: [binsize: 2 max: 371 count: 6772 average: 36.4135 | standard deviation: 69.5949 | 0 5483 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 4 2 2 10 2 309 224 133 323 144 9 3 1 0 0 11 11 1 16 4 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 25 14 6 15 3 1 1 1 0 0 1 1 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_1: [binsize: 2 max: 285 count: 5383 average: 26.3539 | standard deviation: 60.2129 | 0 4668 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 1 0 5 2 172 118 76 168 91 3 1 1 0 0 8 9 0 10 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 18 3 4 10 1 0 0 1 0 0 1 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_2: [binsize: 2 max: 285 count: 716 average: 98.7235 | standard deviation: 87.4535 | 0 321 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 1 2 3 0 110 62 31 116 36 4 1 0 0 0 1 0 1 6 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 5 2 2 3 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_3: [binsize: 2 max: 371 count: 673 average: 50.584 | standard deviation: 80.4924 | 0 494 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 27 44 26 39 17 2 1 0 0 0 2 2 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 9 0 2 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_IFETCH: [binsize: 2 max: 285 count: 5383 average: 26.3539 | standard deviation: 60.2129 | 0 4668 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 1 0 5 2 172 118 76 168 91 3 1 1 0 0 8 9 0 10 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 18 3 4 10 1 0 0 1 0 0 1 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_LD: [binsize: 2 max: 285 count: 716 average: 98.7235 | standard deviation: 87.4535 | 0 321 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 1 2 3 0 110 62 31 116 36 4 1 0 0 0 1 0 1 6 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 5 2 2 3 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST: [binsize: 2 max: 371 count: 673 average: 50.584 | standard deviation: 80.4924 | 0 494 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 27 44 26 39 17 2 1 0 0 0 2 2 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 9 0 2 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_L1Cache: [binsize: 1 max: 3 count: 5483 average: 3 | standard deviation: 0 | 0 0 0 5483 ]
|
||||
miss_latency_Directory: [binsize: 2 max: 371 count: 1289 average: 178.544 | standard deviation: 22.1923 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 4 2 2 10 2 309 224 133 323 144 9 3 1 0 0 11 11 1 16 4 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 25 14 6 15 3 1 1 1 0 0 1 1 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
imcomplete_wCC_Times: 0
|
||||
miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
|
||||
miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
|
||||
miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
|
||||
miss_latency_dir_first_response_to_completion: [binsize: 1 max: 159 count: 1 average: 159 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
imcomplete_dir_Times: 1288
|
||||
miss_latency_IFETCH_L1Cache: [binsize: 1 max: 3 count: 4668 average: 3 | standard deviation: 0 | 0 0 0 4668 ]
|
||||
miss_latency_IFETCH_Directory: [binsize: 2 max: 285 count: 715 average: 178.824 | standard deviation: 21.9931 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 1 0 5 2 172 118 76 168 91 3 1 1 0 0 8 9 0 10 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 18 3 4 10 1 0 0 1 0 0 1 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_LD_L1Cache: [binsize: 1 max: 3 count: 321 average: 3 | standard deviation: 0 | 0 0 0 321 ]
|
||||
miss_latency_LD_Directory: [binsize: 2 max: 285 count: 395 average: 176.514 | standard deviation: 18.6332 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 1 2 3 0 110 62 31 116 36 4 1 0 0 0 1 0 1 6 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 5 2 2 3 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST_L1Cache: [binsize: 1 max: 3 count: 494 average: 3 | standard deviation: 0 | 0 0 0 494 ]
|
||||
miss_latency_ST_Directory: [binsize: 2 max: 371 count: 179 average: 181.905 | standard deviation: 28.882 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 27 44 26 39 17 2 1 0 0 0 2 2 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 9 0 2 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
|
||||
All Non-Zero Cycle SW Prefetch Requests
|
||||
------------------------------------
|
||||
@@ -120,25 +122,31 @@ Resource Usage
|
||||
page_size: 4096
|
||||
user_time: 0
|
||||
system_time: 0
|
||||
page_reclaims: 7494
|
||||
page_faults: 2200
|
||||
page_reclaims: 11225
|
||||
page_faults: 3
|
||||
swaps: 0
|
||||
block_inputs: 0
|
||||
block_outputs: 0
|
||||
block_inputs: 1280
|
||||
block_outputs: 64
|
||||
|
||||
Network Stats
|
||||
-------------
|
||||
|
||||
total_msg_count_Control: 3867 30936
|
||||
total_msg_count_Data: 3855 277560
|
||||
total_msg_count_Response_Data: 3867 278424
|
||||
total_msg_count_Writeback_Control: 3855 30840
|
||||
total_msgs: 15444 total_bytes: 617760
|
||||
|
||||
switch_0_inlinks: 2
|
||||
switch_0_outlinks: 2
|
||||
links_utilized_percent_switch_0: 0.158621
|
||||
links_utilized_percent_switch_0_link_0: 0.0635745 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 0.253667 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_0_link_0_Response_Data: 1289 92808 [ 0 1289 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Writeback_Control: 1285 10280 [ 0 0 1285 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Control: 1289 10312 [ 1289 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Data: 1285 92520 [ 1285 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Response_Data: 1289 92808 [ 0 0 0 0 1289 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Writeback_Control: 1285 10280 [ 0 0 0 1285 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Control: 1289 10312 [ 0 0 1289 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Data: 1285 92520 [ 0 0 1285 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_1_inlinks: 2
|
||||
switch_1_outlinks: 2
|
||||
@@ -146,10 +154,10 @@ links_utilized_percent_switch_1: 0.158857
|
||||
links_utilized_percent_switch_1_link_0: 0.0634167 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 0.254298 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_1_link_0_Control: 1289 10312 [ 1289 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Data: 1285 92520 [ 1285 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Data: 1289 92808 [ 0 1289 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Writeback_Control: 1285 10280 [ 0 0 1285 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Control: 1289 10312 [ 0 0 1289 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Data: 1285 92520 [ 0 0 1285 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Data: 1289 92808 [ 0 0 0 0 1289 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Writeback_Control: 1285 10280 [ 0 0 0 1285 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_2_inlinks: 2
|
||||
switch_2_outlinks: 2
|
||||
@@ -157,63 +165,64 @@ links_utilized_percent_switch_2: 0.253982
|
||||
links_utilized_percent_switch_2_link_0: 0.254298 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 0.253667 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_2_link_0_Response_Data: 1289 92808 [ 0 1289 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Control: 1285 10280 [ 0 0 1285 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Control: 1289 10312 [ 1289 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Data: 1285 92520 [ 1285 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Response_Data: 1289 92808 [ 0 0 0 0 1289 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Control: 1285 10280 [ 0 0 0 1285 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Control: 1289 10312 [ 0 0 1289 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Data: 1285 92520 [ 0 0 1285 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 1289
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 1289
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_misses_per_transaction: inf
|
||||
Cache Stats: system.ruby.cpu_ruby_ports.dcache
|
||||
system.ruby.cpu_ruby_ports.dcache_total_misses: 1289
|
||||
system.ruby.cpu_ruby_ports.dcache_total_demand_misses: 1289
|
||||
system.ruby.cpu_ruby_ports.dcache_total_prefetches: 0
|
||||
system.ruby.cpu_ruby_ports.dcache_total_sw_prefetches: 0
|
||||
system.ruby.cpu_ruby_ports.dcache_total_hw_prefetches: 0
|
||||
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_LD: 30.6439%
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_ST: 13.8867%
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_IFETCH: 55.4694%
|
||||
system.ruby.cpu_ruby_ports.dcache_request_type_LD: 30.6439%
|
||||
system.ruby.cpu_ruby_ports.dcache_request_type_ST: 13.8867%
|
||||
system.ruby.cpu_ruby_ports.dcache_request_type_IFETCH: 55.4694%
|
||||
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_access_mode_type_SupervisorMode: 1289 100%
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 8 count: 1289 average: 5.1249 | standard deviation: 2.01759 | 0 50 2 0 836 0 0 0 401 ]
|
||||
system.ruby.cpu_ruby_ports.dcache_access_mode_type_SupervisorMode: 1289 100%
|
||||
|
||||
--- L1Cache 0 ---
|
||||
--- L1Cache ---
|
||||
- Event Counts -
|
||||
Load 716
|
||||
Ifetch 5383
|
||||
Store 673
|
||||
Data 1289
|
||||
Fwd_GETX 0
|
||||
Inv 0
|
||||
Replacement 1285
|
||||
Writeback_Ack 1285
|
||||
Writeback_Nack 0
|
||||
Load [716 ] 716
|
||||
Ifetch [5383 ] 5383
|
||||
Store [673 ] 673
|
||||
Data [1289 ] 1289
|
||||
Fwd_GETX [0 ] 0
|
||||
Inv [0 ] 0
|
||||
Replacement [1285 ] 1285
|
||||
Writeback_Ack [1285 ] 1285
|
||||
Writeback_Nack [0 ] 0
|
||||
|
||||
- Transitions -
|
||||
I Load 395
|
||||
I Ifetch 715
|
||||
I Store 179
|
||||
I Inv 0 <--
|
||||
I Replacement 0 <--
|
||||
I Load [395 ] 395
|
||||
I Ifetch [715 ] 715
|
||||
I Store [179 ] 179
|
||||
I Inv [0 ] 0
|
||||
I Replacement [0 ] 0
|
||||
|
||||
II Writeback_Nack 0 <--
|
||||
II Writeback_Nack [0 ] 0
|
||||
|
||||
M Load 321
|
||||
M Ifetch 4668
|
||||
M Store 494
|
||||
M Fwd_GETX 0 <--
|
||||
M Inv 0 <--
|
||||
M Replacement 1285
|
||||
M Load [321 ] 321
|
||||
M Ifetch [4668 ] 4668
|
||||
M Store [494 ] 494
|
||||
M Fwd_GETX [0 ] 0
|
||||
M Inv [0 ] 0
|
||||
M Replacement [1285 ] 1285
|
||||
|
||||
MI Fwd_GETX 0 <--
|
||||
MI Inv 0 <--
|
||||
MI Writeback_Ack 1285
|
||||
MI Fwd_GETX [0 ] 0
|
||||
MI Inv [0 ] 0
|
||||
MI Writeback_Ack [1285 ] 1285
|
||||
MI Writeback_Nack [0 ] 0
|
||||
|
||||
IS Data 1110
|
||||
MII Fwd_GETX [0 ] 0
|
||||
|
||||
IM Data 179
|
||||
IS Data [1110 ] 1110
|
||||
|
||||
Memory controller: system.ruby.network.topology.ext_links1.ext_node.memBuffer:
|
||||
IM Data [179 ] 179
|
||||
|
||||
Memory controller: system.dir_cntrl0.memBuffer:
|
||||
memory_total_requests: 2574
|
||||
memory_reads: 1289
|
||||
memory_writes: 1285
|
||||
@@ -233,70 +242,69 @@ Memory controller: system.ruby.network.topology.ext_links1.ext_node.memBuffer:
|
||||
memory_stalls_for_read_read_turnaround: 0
|
||||
accesses_per_bank: 166 40 36 48 109 42 63 241 50 34 16 26 60 64 38 46 30 88 202 144 40 58 22 20 60 120 136 125 84 134 166 66
|
||||
|
||||
--- Directory 0 ---
|
||||
--- Directory ---
|
||||
- Event Counts -
|
||||
GETX 1289
|
||||
GETS 0
|
||||
PUTX 1285
|
||||
PUTX_NotOwner 0
|
||||
DMA_READ 0
|
||||
DMA_WRITE 0
|
||||
Memory_Data 1289
|
||||
Memory_Ack 1285
|
||||
GETX [1289 ] 1289
|
||||
GETS [0 ] 0
|
||||
PUTX [1285 ] 1285
|
||||
PUTX_NotOwner [0 ] 0
|
||||
DMA_READ [0 ] 0
|
||||
DMA_WRITE [0 ] 0
|
||||
Memory_Data [1289 ] 1289
|
||||
Memory_Ack [1285 ] 1285
|
||||
|
||||
- Transitions -
|
||||
I GETX 1289
|
||||
I PUTX_NotOwner 0 <--
|
||||
I DMA_READ 0 <--
|
||||
I DMA_WRITE 0 <--
|
||||
I GETX [1289 ] 1289
|
||||
I PUTX_NotOwner [0 ] 0
|
||||
I DMA_READ [0 ] 0
|
||||
I DMA_WRITE [0 ] 0
|
||||
|
||||
M GETX 0 <--
|
||||
M PUTX 1285
|
||||
M PUTX_NotOwner 0 <--
|
||||
M DMA_READ 0 <--
|
||||
M DMA_WRITE 0 <--
|
||||
M GETX [0 ] 0
|
||||
M PUTX [1285 ] 1285
|
||||
M PUTX_NotOwner [0 ] 0
|
||||
M DMA_READ [0 ] 0
|
||||
M DMA_WRITE [0 ] 0
|
||||
|
||||
M_DRD GETX 0 <--
|
||||
M_DRD PUTX 0 <--
|
||||
M_DRD GETX [0 ] 0
|
||||
M_DRD PUTX [0 ] 0
|
||||
|
||||
M_DWR GETX 0 <--
|
||||
M_DWR PUTX 0 <--
|
||||
M_DWR GETX [0 ] 0
|
||||
M_DWR PUTX [0 ] 0
|
||||
|
||||
M_DWRI GETX 0 <--
|
||||
M_DWRI Memory_Ack 0 <--
|
||||
M_DWRI GETX [0 ] 0
|
||||
M_DWRI Memory_Ack [0 ] 0
|
||||
|
||||
M_DRDI GETX 0 <--
|
||||
M_DRDI Memory_Ack 0 <--
|
||||
M_DRDI GETX [0 ] 0
|
||||
M_DRDI Memory_Ack [0 ] 0
|
||||
|
||||
IM GETX 0 <--
|
||||
IM GETS 0 <--
|
||||
IM PUTX 0 <--
|
||||
IM PUTX_NotOwner 0 <--
|
||||
IM DMA_READ 0 <--
|
||||
IM DMA_WRITE 0 <--
|
||||
IM Memory_Data 1289
|
||||
IM GETX [0 ] 0
|
||||
IM GETS [0 ] 0
|
||||
IM PUTX [0 ] 0
|
||||
IM PUTX_NotOwner [0 ] 0
|
||||
IM DMA_READ [0 ] 0
|
||||
IM DMA_WRITE [0 ] 0
|
||||
IM Memory_Data [1289 ] 1289
|
||||
|
||||
MI GETX 0 <--
|
||||
MI GETS 0 <--
|
||||
MI PUTX 0 <--
|
||||
MI PUTX_NotOwner 0 <--
|
||||
MI DMA_READ 0 <--
|
||||
MI DMA_WRITE 0 <--
|
||||
MI Memory_Ack 1285
|
||||
MI GETX [0 ] 0
|
||||
MI GETS [0 ] 0
|
||||
MI PUTX [0 ] 0
|
||||
MI PUTX_NotOwner [0 ] 0
|
||||
MI DMA_READ [0 ] 0
|
||||
MI DMA_WRITE [0 ] 0
|
||||
MI Memory_Ack [1285 ] 1285
|
||||
|
||||
ID GETX 0 <--
|
||||
ID GETS 0 <--
|
||||
ID PUTX 0 <--
|
||||
ID PUTX_NotOwner 0 <--
|
||||
ID DMA_READ 0 <--
|
||||
ID DMA_WRITE 0 <--
|
||||
ID Memory_Data 0 <--
|
||||
|
||||
ID_W GETX 0 <--
|
||||
ID_W GETS 0 <--
|
||||
ID_W PUTX 0 <--
|
||||
ID_W PUTX_NotOwner 0 <--
|
||||
ID_W DMA_READ 0 <--
|
||||
ID_W DMA_WRITE 0 <--
|
||||
ID_W Memory_Ack 0 <--
|
||||
ID GETX [0 ] 0
|
||||
ID GETS [0 ] 0
|
||||
ID PUTX [0 ] 0
|
||||
ID PUTX_NotOwner [0 ] 0
|
||||
ID DMA_READ [0 ] 0
|
||||
ID DMA_WRITE [0 ] 0
|
||||
ID Memory_Data [0 ] 0
|
||||
|
||||
ID_W GETX [0 ] 0
|
||||
ID_W GETS [0 ] 0
|
||||
ID_W PUTX [0 ] 0
|
||||
ID_W PUTX_NotOwner [0 ] 0
|
||||
ID_W DMA_READ [0 ] 0
|
||||
ID_W DMA_WRITE [0 ] 0
|
||||
ID_W Memory_Ack
|
||||
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jan 21 2010 11:29:25
|
||||
M5 revision a2fac757fb31+ 6860+ default qtip brad/rubycfg_orion_update tip
|
||||
M5 started Jan 21 2010 11:30:48
|
||||
M5 executing on svvint07
|
||||
M5 compiled Feb 7 2011 02:13:30
|
||||
M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
|
||||
M5 started Feb 7 2011 02:13:38
|
||||
M5 executing on burrito
|
||||
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing-ruby -re tests/run.py build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing-ruby
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
@@ -1,9 +1,9 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 59331 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 347024 # Number of bytes of host memory used
|
||||
host_seconds 0.09 # Real time elapsed on the host
|
||||
host_tick_rate 2815062 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 26190 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 233840 # Number of bytes of host memory used
|
||||
host_seconds 0.20 # Real time elapsed on the host
|
||||
host_tick_rate 1241276 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
sim_insts 5340 # Number of instructions simulated
|
||||
sim_seconds 0.000253 # Number of seconds simulated
|
||||
@@ -11,8 +11,24 @@ sim_ticks 253364 # Nu
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 253364 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.num_busy_cycles 253364 # Number of busy cycles
|
||||
system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls
|
||||
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
|
||||
system.cpu.num_fp_insts 0 # number of float instructions
|
||||
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu.num_func_calls 0 # number of times a function call or return occured
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_insts 5340 # Number of instructions executed
|
||||
system.cpu.num_refs 1402 # Number of memory references
|
||||
system.cpu.num_int_alu_accesses 4517 # Number of integer alu accesses
|
||||
system.cpu.num_int_insts 4517 # number of integer instructions
|
||||
system.cpu.num_int_register_reads 10620 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 4858 # number of times the integer registers were written
|
||||
system.cpu.num_load_insts 724 # Number of load instructions
|
||||
system.cpu.num_mem_refs 1402 # number of memory refs
|
||||
system.cpu.num_store_insts 678 # Number of store instructions
|
||||
system.cpu.workload.PROG:num_syscalls 11 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
||||
@@ -1,13 +1,22 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
dummy=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
mem_mode=atomic
|
||||
physmem=system.physmem
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
|
||||
@@ -1,5 +1,3 @@
|
||||
Redirecting stdout to build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/simple-timing/simout
|
||||
Redirecting stderr to build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/simple-timing/simerr
|
||||
M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2008
|
||||
@@ -7,11 +5,11 @@ The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Aug 26 2010 13:03:41
|
||||
M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
|
||||
M5 started Aug 26 2010 13:05:08
|
||||
M5 executing on zizzer
|
||||
command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/simple-timing
|
||||
M5 compiled Feb 7 2011 02:13:30
|
||||
M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
|
||||
M5 started Feb 7 2011 02:14:00
|
||||
M5 executing on burrito
|
||||
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Hello World!Exiting @ tick 28206000 because target called exit()
|
||||
|
||||
@@ -1,9 +1,9 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 369934 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 207380 # Number of bytes of host memory used
|
||||
host_seconds 0.01 # Real time elapsed on the host
|
||||
host_tick_rate 1923223783 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 87383 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 223480 # Number of bytes of host memory used
|
||||
host_seconds 0.06 # Real time elapsed on the host
|
||||
host_tick_rate 459485360 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 5340 # Number of instructions simulated
|
||||
sim_seconds 0.000028 # Number of seconds simulated
|
||||
@@ -195,8 +195,24 @@ system.cpu.l2cache.warmup_cycle 0 # Cy
|
||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 56412 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.num_busy_cycles 56412 # Number of busy cycles
|
||||
system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls
|
||||
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
|
||||
system.cpu.num_fp_insts 0 # number of float instructions
|
||||
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu.num_func_calls 0 # number of times a function call or return occured
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_insts 5340 # Number of instructions executed
|
||||
system.cpu.num_refs 1402 # Number of memory references
|
||||
system.cpu.num_int_alu_accesses 4517 # Number of integer alu accesses
|
||||
system.cpu.num_int_insts 4517 # number of integer instructions
|
||||
system.cpu.num_int_register_reads 10620 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 4858 # number of times the integer registers were written
|
||||
system.cpu.num_load_insts 724 # Number of load instructions
|
||||
system.cpu.num_mem_refs 1402 # number of memory refs
|
||||
system.cpu.num_store_insts 678 # Number of store instructions
|
||||
system.cpu.workload.PROG:num_syscalls 11 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
||||
@@ -10,6 +10,13 @@ type=System
|
||||
children=cpu membus physmem
|
||||
mem_mode=atomic
|
||||
physmem=system.physmem
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
|
||||
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jan 31 2011 16:34:44
|
||||
M5 revision 1b98eea40540 7883 default qtip tip x86o3regressions.patch
|
||||
M5 started Jan 31 2011 16:34:46
|
||||
M5 compiled Feb 7 2011 02:32:07
|
||||
M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
|
||||
M5 started Feb 7 2011 02:32:13
|
||||
M5 executing on burrito
|
||||
command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/quick/00.hello/x86/linux/o3-timing
|
||||
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Hello world!
|
||||
|
||||
@@ -1,9 +1,9 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 48300 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 226820 # Number of bytes of host memory used
|
||||
host_seconds 0.20 # Real time elapsed on the host
|
||||
host_tick_rate 67673766 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 47133 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 227692 # Number of bytes of host memory used
|
||||
host_seconds 0.21 # Real time elapsed on the host
|
||||
host_tick_rate 66053082 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 9809 # Number of instructions simulated
|
||||
sim_seconds 0.000014 # Number of seconds simulated
|
||||
@@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value 0
|
||||
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::total 15124 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:count 9809 # Number of instructions committed
|
||||
system.cpu.commit.COM:fp_insts 0 # Number of committed floating point instructions.
|
||||
system.cpu.commit.COM:function_calls 0 # Number of function calls committed.
|
||||
system.cpu.commit.COM:int_insts 9714 # Number of committed integer instructions.
|
||||
system.cpu.commit.COM:loads 1056 # Number of loads committed
|
||||
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
|
||||
system.cpu.commit.COM:refs 1990 # Number of memory references committed
|
||||
@@ -150,6 +153,7 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 15845 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fp_regfile_reads 2 # number of floating regfile reads
|
||||
system.cpu.icache.ReadReq_accesses 1255 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 37417.543860 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35040.697674 # average ReadReq mshr miss latency
|
||||
@@ -249,6 +253,8 @@ system.cpu.iew.lsq.thread.0.squashedStores 304 #
|
||||
system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 390 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 97 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.int_regfile_reads 25083 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 11189 # number of integer regfile writes
|
||||
system.cpu.ipc 0.356263 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.356263 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 3 0.02% 0.02% # Type of FU issued
|
||||
@@ -340,6 +346,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value 0
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::max_value 6 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::total 15845 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:rate 0.454146 # Inst issue rate
|
||||
system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_writes 8 # Number of floating instruction queue writes
|
||||
system.cpu.iq.int_alu_accesses 12501 # Number of integer alu accesses
|
||||
system.cpu.iq.int_inst_queue_reads 40849 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 11816 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.int_inst_queue_writes 16975 # Number of integer instruction queue writes
|
||||
system.cpu.iq.iqInstsAdded 13618 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 12504 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 17 # Number of non-speculative instructions added to the IQ
|
||||
@@ -414,7 +428,10 @@ system.cpu.memDep0.conflictingLoads 4 # Nu
|
||||
system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
|
||||
system.cpu.memDep0.insertedLoads 1535 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 1238 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.misc_regfile_reads 5334 # number of misc regfile reads
|
||||
system.cpu.numCycles 27533 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.rename.RENAME:BlockCycles 105 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:CommittedMaps 9368 # Number of HB maps that are committed
|
||||
system.cpu.rename.RENAME:IQFullEvents 6 # Number of times rename has blocked due to IQ full
|
||||
@@ -427,10 +444,14 @@ system.cpu.rename.RENAME:RunCycles 8027 # Nu
|
||||
system.cpu.rename.RENAME:SquashCycles 721 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 108 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 4419 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:fp_rename_lookups 16 # Number of floating rename lookups
|
||||
system.cpu.rename.RENAME:int_rename_lookups 38648 # Number of integer rename lookups
|
||||
system.cpu.rename.RENAME:serializeStallCycles 281 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 20 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 169 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 17 # count of temporary serializing insts renamed
|
||||
system.cpu.rob.rob_reads 28728 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 28005 # The number of ROB writes
|
||||
system.cpu.timesIdled 208 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.workload.PROG:num_syscalls 11 # Number of system calls
|
||||
|
||||
|
||||
@@ -10,6 +10,13 @@ type=System
|
||||
children=cpu membus physmem
|
||||
mem_mode=atomic
|
||||
physmem=system.physmem
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
|
||||
[system.cpu]
|
||||
type=AtomicSimpleCPU
|
||||
|
||||
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jan 31 2011 14:03:49
|
||||
M5 revision aa283c8952a9 7880 default qtip stupdstats.patch tip
|
||||
M5 started Jan 31 2011 14:03:51
|
||||
M5 compiled Feb 7 2011 02:32:07
|
||||
M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
|
||||
M5 started Feb 7 2011 02:32:13
|
||||
M5 executing on burrito
|
||||
command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-atomic
|
||||
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Hello world!
|
||||
|
||||
@@ -1,9 +1,9 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 137874 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 215488 # Number of bytes of host memory used
|
||||
host_seconds 0.07 # Real time elapsed on the host
|
||||
host_tick_rate 79078853 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 180423 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 219128 # Number of bytes of host memory used
|
||||
host_seconds 0.05 # Real time elapsed on the host
|
||||
host_tick_rate 103433649 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 9810 # Number of instructions simulated
|
||||
sim_seconds 0.000006 # Number of seconds simulated
|
||||
@@ -11,8 +11,24 @@ sim_ticks 5651000 # Nu
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 11303 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.num_busy_cycles 11303 # Number of busy cycles
|
||||
system.cpu.num_conditional_control_insts 904 # number of instructions that are conditional controls
|
||||
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
|
||||
system.cpu.num_fp_insts 0 # number of float instructions
|
||||
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu.num_func_calls 0 # number of times a function call or return occured
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_insts 9810 # Number of instructions executed
|
||||
system.cpu.num_refs 1990 # Number of memory references
|
||||
system.cpu.num_int_alu_accesses 9715 # Number of integer alu accesses
|
||||
system.cpu.num_int_insts 9715 # number of integer instructions
|
||||
system.cpu.num_int_register_reads 26194 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 9368 # number of times the integer registers were written
|
||||
system.cpu.num_load_insts 1056 # Number of load instructions
|
||||
system.cpu.num_mem_refs 1990 # number of memory refs
|
||||
system.cpu.num_store_insts 934 # Number of store instructions
|
||||
system.cpu.workload.PROG:num_syscalls 11 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
||||
@@ -10,6 +10,13 @@ type=System
|
||||
children=cpu dir_cntrl0 l1_cntrl0 physmem ruby
|
||||
mem_mode=timing
|
||||
physmem=system.physmem
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
@@ -147,6 +154,7 @@ tracer=system.ruby.tracer
|
||||
[system.ruby.cpu_ruby_ports]
|
||||
type=RubySequencer
|
||||
children=dcache
|
||||
access_phys_mem=true
|
||||
dcache=system.ruby.cpu_ruby_ports.dcache
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.cpu_ruby_ports.dcache
|
||||
|
||||
@@ -34,7 +34,7 @@ periodic_stats_period: 1000000
|
||||
================ End RubySystem Configuration Print ================
|
||||
|
||||
|
||||
Real time: Feb/04/2011 03:47:05
|
||||
Real time: Feb/07/2011 02:32:13
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
@@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0
|
||||
Elapsed_time_in_hours: 0
|
||||
Elapsed_time_in_days: 0
|
||||
|
||||
Virtual_time_in_seconds: 0.19
|
||||
Virtual_time_in_minutes: 0.00316667
|
||||
Virtual_time_in_hours: 5.27778e-05
|
||||
Virtual_time_in_days: 2.19907e-06
|
||||
Virtual_time_in_seconds: 0.35
|
||||
Virtual_time_in_minutes: 0.00583333
|
||||
Virtual_time_in_hours: 9.72222e-05
|
||||
Virtual_time_in_days: 4.05093e-06
|
||||
|
||||
Ruby_current_time: 276484
|
||||
Ruby_start_time: 0
|
||||
Ruby_cycles: 276484
|
||||
|
||||
mbytes_resident: 38.8594
|
||||
mbytes_total: 233.992
|
||||
resident_ratio: 0.166088
|
||||
mbytes_resident: 38.6094
|
||||
mbytes_total: 231.508
|
||||
resident_ratio: 0.16679
|
||||
|
||||
ruby_cycles_executed: [ 276485 ]
|
||||
|
||||
@@ -71,8 +71,9 @@ All Non-Zero Cycle Demand Cache Accesses
|
||||
----------------------------------------
|
||||
miss_latency: [binsize: 2 max: 371 count: 8900 average: 30.0656 | standard deviation: 63.8436 | 0 7523 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 9 4 1 3 2 328 243 178 299 187 7 4 1 3 0 8 6 4 9 5 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 6 11 19 16 9 0 1 0 1 1 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 ]
|
||||
miss_latency_IFETCH: [binsize: 2 max: 369 count: 6910 average: 18.6938 | standard deviation: 50.1996 | 0 6287 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 2 2 0 1 0 158 125 57 116 102 5 3 0 2 0 8 5 3 4 4 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 2 3 8 6 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_LD: [binsize: 2 max: 293 count: 1056 average: 86.3144 | standard deviation: 89.2896 | 0 556 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 5 1 1 1 1 104 47 87 151 61 1 0 0 1 0 0 1 0 4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 3 1 14 8 2 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_LD: [binsize: 2 max: 293 count: 1048 average: 86.792 | standard deviation: 89.333 | 0 549 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 5 1 1 1 1 103 47 87 151 61 1 0 0 1 0 0 1 0 4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 3 1 14 8 2 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST: [binsize: 2 max: 371 count: 934 average: 50.6017 | standard deviation: 78.9939 | 0 680 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 1 0 1 1 66 71 34 32 24 1 1 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 8 2 0 1 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_RMW_Read: [binsize: 1 max: 169 count: 8 average: 23.75 | standard deviation: 58.6905 | 0 0 0 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_L1Cache: [binsize: 1 max: 3 count: 7523 average: 3 | standard deviation: 0 | 0 0 0 7523 ]
|
||||
miss_latency_Directory: [binsize: 2 max: 371 count: 1377 average: 177.934 | standard deviation: 21.7881 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 9 4 1 3 2 328 243 178 299 187 7 4 1 3 0 8 6 4 9 5 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 6 11 19 16 9 0 1 0 1 1 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 ]
|
||||
miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
@@ -87,10 +88,12 @@ miss_latency_dir_first_response_to_completion: [binsize: 1 max: 159 count: 1 ave
|
||||
imcomplete_dir_Times: 1376
|
||||
miss_latency_IFETCH_L1Cache: [binsize: 1 max: 3 count: 6287 average: 3 | standard deviation: 0 | 0 0 0 6287 ]
|
||||
miss_latency_IFETCH_Directory: [binsize: 2 max: 369 count: 623 average: 177.067 | standard deviation: 19.4782 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 2 2 0 1 0 158 125 57 116 102 5 3 0 2 0 8 5 3 4 4 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 2 3 8 6 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_LD_L1Cache: [binsize: 1 max: 3 count: 556 average: 3 | standard deviation: 0 | 0 0 0 556 ]
|
||||
miss_latency_LD_Directory: [binsize: 2 max: 293 count: 500 average: 178.96 | standard deviation: 22.8334 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 5 1 1 1 1 104 47 87 151 61 1 0 0 1 0 0 1 0 4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 3 1 14 8 2 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_LD_L1Cache: [binsize: 1 max: 3 count: 549 average: 3 | standard deviation: 0 | 0 0 0 549 ]
|
||||
miss_latency_LD_Directory: [binsize: 2 max: 293 count: 499 average: 178.98 | standard deviation: 22.8519 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 5 1 1 1 1 103 47 87 151 61 1 0 0 1 0 0 1 0 4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 3 1 14 8 2 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST_L1Cache: [binsize: 1 max: 3 count: 680 average: 3 | standard deviation: 0 | 0 0 0 680 ]
|
||||
miss_latency_ST_Directory: [binsize: 2 max: 371 count: 254 average: 178.039 | standard deviation: 24.8377 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 1 0 1 1 66 71 34 32 24 1 1 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 8 2 0 1 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_RMW_Read_L1Cache: [binsize: 1 max: 3 count: 7 average: 3 | standard deviation: 0 | 0 0 0 7 ]
|
||||
miss_latency_RMW_Read_Directory: [binsize: 1 max: 169 count: 1 average: 169 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
|
||||
All Non-Zero Cycle SW Prefetch Requests
|
||||
------------------------------------
|
||||
@@ -122,7 +125,7 @@ Resource Usage
|
||||
page_size: 4096
|
||||
user_time: 0
|
||||
system_time: 0
|
||||
page_reclaims: 11021
|
||||
page_reclaims: 10950
|
||||
page_faults: 0
|
||||
swaps: 0
|
||||
block_inputs: 0
|
||||
@@ -177,17 +180,17 @@ Cache Stats: system.ruby.cpu_ruby_ports.dcache
|
||||
system.ruby.cpu_ruby_ports.dcache_total_sw_prefetches: 0
|
||||
system.ruby.cpu_ruby_ports.dcache_total_hw_prefetches: 0
|
||||
|
||||
system.ruby.cpu_ruby_ports.dcache_request_type_LD: 36.3108%
|
||||
system.ruby.cpu_ruby_ports.dcache_request_type_ST: 18.4459%
|
||||
system.ruby.cpu_ruby_ports.dcache_request_type_LD: 36.2382%
|
||||
system.ruby.cpu_ruby_ports.dcache_request_type_ST: 18.5185%
|
||||
system.ruby.cpu_ruby_ports.dcache_request_type_IFETCH: 45.2433%
|
||||
|
||||
system.ruby.cpu_ruby_ports.dcache_access_mode_type_SupervisorMode: 1377 100%
|
||||
|
||||
--- L1Cache ---
|
||||
- Event Counts -
|
||||
Load [1056 ] 1056
|
||||
Load [1048 ] 1048
|
||||
Ifetch [6910 ] 6910
|
||||
Store [934 ] 934
|
||||
Store [942 ] 942
|
||||
Data [1377 ] 1377
|
||||
Fwd_GETX [0 ] 0
|
||||
Inv [0 ] 0
|
||||
@@ -196,17 +199,17 @@ Writeback_Ack [1373 ] 1373
|
||||
Writeback_Nack [0 ] 0
|
||||
|
||||
- Transitions -
|
||||
I Load [500 ] 500
|
||||
I Load [499 ] 499
|
||||
I Ifetch [623 ] 623
|
||||
I Store [254 ] 254
|
||||
I Store [255 ] 255
|
||||
I Inv [0 ] 0
|
||||
I Replacement [0 ] 0
|
||||
|
||||
II Writeback_Nack [0 ] 0
|
||||
|
||||
M Load [556 ] 556
|
||||
M Load [549 ] 549
|
||||
M Ifetch [6287 ] 6287
|
||||
M Store [680 ] 680
|
||||
M Store [687 ] 687
|
||||
M Fwd_GETX [0 ] 0
|
||||
M Inv [0 ] 0
|
||||
M Replacement [1373 ] 1373
|
||||
@@ -218,9 +221,9 @@ MI Writeback_Nack [0 ] 0
|
||||
|
||||
MII Fwd_GETX [0 ] 0
|
||||
|
||||
IS Data [1123 ] 1123
|
||||
IS Data [1122 ] 1122
|
||||
|
||||
IM Data [254 ] 254
|
||||
IM Data [255 ] 255
|
||||
|
||||
Memory controller: system.dir_cntrl0.memBuffer:
|
||||
memory_total_requests: 2750
|
||||
|
||||
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Feb 4 2011 03:47:02
|
||||
M5 revision afcc4492291f 7892 default qbase qtip rubystatupdate.patch tip
|
||||
M5 started Feb 4 2011 03:47:05
|
||||
M5 compiled Feb 7 2011 02:32:07
|
||||
M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
|
||||
M5 started Feb 7 2011 02:32:13
|
||||
M5 executing on burrito
|
||||
command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing-ruby -re tests/run.py build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing-ruby
|
||||
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing-ruby -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing-ruby
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Hello world!
|
||||
|
||||
@@ -1,9 +1,9 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 106685 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 239612 # Number of bytes of host memory used
|
||||
host_seconds 0.09 # Real time elapsed on the host
|
||||
host_tick_rate 3002497 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 32378 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 237068 # Number of bytes of host memory used
|
||||
host_seconds 0.30 # Real time elapsed on the host
|
||||
host_tick_rate 911908 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
sim_insts 9810 # Number of instructions simulated
|
||||
sim_seconds 0.000276 # Number of seconds simulated
|
||||
@@ -11,8 +11,24 @@ sim_ticks 276484 # Nu
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 276484 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.num_busy_cycles 276484 # Number of busy cycles
|
||||
system.cpu.num_conditional_control_insts 904 # number of instructions that are conditional controls
|
||||
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
|
||||
system.cpu.num_fp_insts 0 # number of float instructions
|
||||
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu.num_func_calls 0 # number of times a function call or return occured
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_insts 9810 # Number of instructions executed
|
||||
system.cpu.num_refs 1990 # Number of memory references
|
||||
system.cpu.num_int_alu_accesses 9715 # Number of integer alu accesses
|
||||
system.cpu.num_int_insts 9715 # number of integer instructions
|
||||
system.cpu.num_int_register_reads 26194 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 9368 # number of times the integer registers were written
|
||||
system.cpu.num_load_insts 1056 # Number of load instructions
|
||||
system.cpu.num_mem_refs 1990 # number of memory refs
|
||||
system.cpu.num_store_insts 934 # Number of store instructions
|
||||
system.cpu.workload.PROG:num_syscalls 11 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
||||
@@ -10,6 +10,13 @@ type=System
|
||||
children=cpu membus physmem
|
||||
mem_mode=atomic
|
||||
physmem=system.physmem
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
|
||||
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jan 31 2011 14:03:49
|
||||
M5 revision aa283c8952a9 7880 default qtip stupdstats.patch tip
|
||||
M5 started Jan 31 2011 14:03:51
|
||||
M5 compiled Feb 7 2011 02:32:07
|
||||
M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
|
||||
M5 started Feb 7 2011 02:32:24
|
||||
M5 executing on burrito
|
||||
command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing
|
||||
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Hello world!
|
||||
|
||||
@@ -1,9 +1,9 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 101671 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 223168 # Number of bytes of host memory used
|
||||
host_seconds 0.10 # Real time elapsed on the host
|
||||
host_tick_rate 297579540 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 594010 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 226844 # Number of bytes of host memory used
|
||||
host_seconds 0.02 # Real time elapsed on the host
|
||||
host_tick_rate 1712507148 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 9810 # Number of instructions simulated
|
||||
sim_seconds 0.000029 # Number of seconds simulated
|
||||
@@ -195,8 +195,24 @@ system.cpu.l2cache.warmup_cycle 0 # Cy
|
||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 57536 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.num_busy_cycles 57536 # Number of busy cycles
|
||||
system.cpu.num_conditional_control_insts 904 # number of instructions that are conditional controls
|
||||
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
|
||||
system.cpu.num_fp_insts 0 # number of float instructions
|
||||
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu.num_func_calls 0 # number of times a function call or return occured
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_insts 9810 # Number of instructions executed
|
||||
system.cpu.num_refs 1990 # Number of memory references
|
||||
system.cpu.num_int_alu_accesses 9715 # Number of integer alu accesses
|
||||
system.cpu.num_int_insts 9715 # number of integer instructions
|
||||
system.cpu.num_int_register_reads 26194 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 9368 # number of times the integer registers were written
|
||||
system.cpu.num_load_insts 1056 # Number of load instructions
|
||||
system.cpu.num_mem_refs 1990 # number of memory refs
|
||||
system.cpu.num_store_insts 934 # Number of store instructions
|
||||
system.cpu.workload.PROG:num_syscalls 11 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
||||
@@ -1,13 +1,22 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
dummy=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
mem_mode=atomic
|
||||
physmem=system.physmem
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
|
||||
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jan 17 2011 16:24:53
|
||||
M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase
|
||||
M5 started Jan 17 2011 16:24:57
|
||||
M5 executing on zizzer
|
||||
M5 compiled Feb 7 2011 01:47:18
|
||||
M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
|
||||
M5 started Feb 7 2011 01:47:39
|
||||
M5 executing on burrito
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
@@ -1,9 +1,9 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 10660 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 204092 # Number of bytes of host memory used
|
||||
host_seconds 1.20 # Real time elapsed on the host
|
||||
host_tick_rate 11797749 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 41761 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 224488 # Number of bytes of host memory used
|
||||
host_seconds 0.31 # Real time elapsed on the host
|
||||
host_tick_rate 46181742 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 12773 # Number of instructions simulated
|
||||
sim_seconds 0.000014 # Number of seconds simulated
|
||||
@@ -43,6 +43,15 @@ system.cpu.commit.COM:committed_per_cycle::total 22158
|
||||
system.cpu.commit.COM:count::0 6404 # Number of instructions committed
|
||||
system.cpu.commit.COM:count::1 6403 # Number of instructions committed
|
||||
system.cpu.commit.COM:count::total 12807 # Number of instructions committed
|
||||
system.cpu.commit.COM:fp_insts::0 10 # Number of committed floating point instructions.
|
||||
system.cpu.commit.COM:fp_insts::1 10 # Number of committed floating point instructions.
|
||||
system.cpu.commit.COM:fp_insts::total 20 # Number of committed floating point instructions.
|
||||
system.cpu.commit.COM:function_calls::0 127 # Number of function calls committed.
|
||||
system.cpu.commit.COM:function_calls::1 127 # Number of function calls committed.
|
||||
system.cpu.commit.COM:function_calls::total 254 # Number of function calls committed.
|
||||
system.cpu.commit.COM:int_insts::0 6321 # Number of committed integer instructions.
|
||||
system.cpu.commit.COM:int_insts::1 6321 # Number of committed integer instructions.
|
||||
system.cpu.commit.COM:int_insts::total 12642 # Number of committed integer instructions.
|
||||
system.cpu.commit.COM:loads::0 1185 # Number of loads committed
|
||||
system.cpu.commit.COM:loads::1 1185 # Number of loads committed
|
||||
system.cpu.commit.COM:loads::total 2370 # Number of loads committed
|
||||
@@ -239,6 +248,8 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 22205 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
|
||||
system.cpu.fp_regfile_writes 4 # number of floating regfile writes
|
||||
system.cpu.icache.ReadReq_accesses 3993 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::0 35767.942584 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 35767.942584 # average ReadReq miss latency
|
||||
@@ -424,6 +435,8 @@ system.cpu.iew.lsq.thread.1.squashedStores 367 #
|
||||
system.cpu.iew.memOrderViolationEvents 131 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 1010 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 260 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.int_regfile_reads 23900 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 13586 # number of integer regfile writes
|
||||
system.cpu.ipc::0 0.225857 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc::1 0.225821 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.451678 # IPC: Total IPC of All Threads
|
||||
@@ -590,6 +603,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value 0
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::total 22205 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:rate 0.703773 # Inst issue rate
|
||||
system.cpu.iq.fp_alu_accesses 22 # Number of floating point alu accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 42 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_writes 20 # Number of floating instruction queue writes
|
||||
system.cpu.iq.int_alu_accesses 20041 # Number of integer alu accesses
|
||||
system.cpu.iq.int_inst_queue_reads 62207 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 18120 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.int_inst_queue_writes 32069 # Number of integer instruction queue writes
|
||||
system.cpu.iq.iqInstsAdded 22957 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 19902 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 46 # Number of non-speculative instructions added to the IQ
|
||||
@@ -737,7 +758,11 @@ system.cpu.memDep1.conflictingLoads 22 # Nu
|
||||
system.cpu.memDep1.conflictingStores 7 # Number of conflicting stores.
|
||||
system.cpu.memDep1.insertedLoads 2368 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep1.insertedStores 1232 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.misc_regfile_reads 2 # number of misc regfile reads
|
||||
system.cpu.misc_regfile_writes 2 # number of misc regfile writes
|
||||
system.cpu.numCycles 28279 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.rename.RENAME:BlockCycles 2728 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:CommittedMaps 9166 # Number of HB maps that are committed
|
||||
system.cpu.rename.RENAME:IQFullEvents 4 # Number of times rename has blocked due to IQ full
|
||||
@@ -751,10 +776,14 @@ system.cpu.rename.RENAME:RunCycles 4411 # Nu
|
||||
system.cpu.rename.RENAME:SquashCycles 2039 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 1326 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 9705 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:fp_rename_lookups 34 # Number of floating rename lookups
|
||||
system.cpu.rename.RENAME:int_rename_lookups 31597 # Number of integer rename lookups
|
||||
system.cpu.rename.RENAME:serializeStallCycles 679 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 50 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 3216 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 38 # count of temporary serializing insts renamed
|
||||
system.cpu.rob.rob_reads 106394 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 48170 # The number of ROB writes
|
||||
system.cpu.timesIdled 276 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.workload0.PROG:num_syscalls 17 # Number of system calls
|
||||
system.cpu.workload1.PROG:num_syscalls 17 # Number of system calls
|
||||
|
||||
@@ -1,13 +1,22 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
dummy=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
mem_mode=atomic
|
||||
physmem=system.physmem
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
|
||||
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jan 17 2011 21:17:52
|
||||
M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase
|
||||
M5 started Jan 17 2011 21:18:06
|
||||
M5 executing on zizzer
|
||||
M5 compiled Feb 7 2011 02:13:30
|
||||
M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
|
||||
M5 started Feb 7 2011 02:13:49
|
||||
M5 executing on burrito
|
||||
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
@@ -1,9 +1,9 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 91156 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 203828 # Number of bytes of host memory used
|
||||
host_seconds 0.16 # Real time elapsed on the host
|
||||
host_tick_rate 117504787 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 30834 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 224180 # Number of bytes of host memory used
|
||||
host_seconds 0.47 # Real time elapsed on the host
|
||||
host_tick_rate 39786625 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 14449 # Number of instructions simulated
|
||||
sim_seconds 0.000019 # Number of seconds simulated
|
||||
@@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value 0
|
||||
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::total 27579 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:count 15175 # Number of instructions committed
|
||||
system.cpu.commit.COM:fp_insts 0 # Number of committed floating point instructions.
|
||||
system.cpu.commit.COM:function_calls 0 # Number of function calls committed.
|
||||
system.cpu.commit.COM:int_insts 12186 # Number of committed integer instructions.
|
||||
system.cpu.commit.COM:loads 2226 # Number of loads committed
|
||||
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
|
||||
system.cpu.commit.COM:refs 3674 # Number of memory references committed
|
||||
@@ -251,6 +254,8 @@ system.cpu.iew.lsq.thread.0.squashedStores 477 #
|
||||
system.cpu.iew.memOrderViolationEvents 54 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 560 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 240 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.int_regfile_reads 28146 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 15679 # number of integer regfile writes
|
||||
system.cpu.ipc 0.387238 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.387238 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
||||
@@ -342,6 +347,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value 0
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::total 28740 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:rate 0.483451 # Inst issue rate
|
||||
system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
|
||||
system.cpu.iq.int_alu_accesses 18164 # Number of integer alu accesses
|
||||
system.cpu.iq.int_inst_queue_reads 65024 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 17128 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.int_inst_queue_writes 23367 # Number of integer instruction queue writes
|
||||
system.cpu.iq.iqInstsAdded 18671 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 18039 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 566 # Number of non-speculative instructions added to the IQ
|
||||
@@ -417,7 +430,11 @@ system.cpu.memDep0.conflictingLoads 13 # Nu
|
||||
system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
|
||||
system.cpu.memDep0.insertedLoads 3058 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 1925 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.misc_regfile_reads 6238 # number of misc regfile reads
|
||||
system.cpu.misc_regfile_writes 569 # number of misc regfile writes
|
||||
system.cpu.numCycles 37313 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.rename.RENAME:BlockCycles 254 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:CommittedMaps 13832 # Number of HB maps that are committed
|
||||
system.cpu.rename.RENAME:IdleCycles 13569 # Number of cycles rename is idle
|
||||
@@ -429,10 +446,13 @@ system.cpu.rename.RENAME:RunCycles 7042 # Nu
|
||||
system.cpu.rename.RENAME:SquashCycles 1178 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 421 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 5696 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:int_rename_lookups 40450 # Number of integer rename lookups
|
||||
system.cpu.rename.RENAME:serializeStallCycles 6276 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 617 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 2691 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 583 # count of temporary serializing insts renamed
|
||||
system.cpu.rob.rob_reads 46980 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 41800 # The number of ROB writes
|
||||
system.cpu.timesIdled 183 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.workload.PROG:num_syscalls 18 # Number of system calls
|
||||
|
||||
|
||||
@@ -1,13 +1,22 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
dummy=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
mem_mode=atomic
|
||||
physmem=system.physmem
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
|
||||
[system.cpu]
|
||||
type=AtomicSimpleCPU
|
||||
@@ -57,7 +66,7 @@ egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/insttest/bin/sparc/linux/insttest
|
||||
executable=/dist/m5/regression/test-progs/insttest/bin/sparc/linux/insttest
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
||||
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Feb 25 2010 03:11:27
|
||||
M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
|
||||
M5 started Feb 25 2010 03:38:01
|
||||
M5 executing on SC2B0619
|
||||
M5 compiled Feb 7 2011 02:13:30
|
||||
M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
|
||||
M5 started Feb 7 2011 02:13:50
|
||||
M5 executing on burrito
|
||||
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-atomic
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
@@ -1,9 +1,9 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 1098364 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 182400 # Number of bytes of host memory used
|
||||
host_seconds 0.01 # Real time elapsed on the host
|
||||
host_tick_rate 540894569 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 73199 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 215552 # Number of bytes of host memory used
|
||||
host_seconds 0.21 # Real time elapsed on the host
|
||||
host_tick_rate 36700023 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 15175 # Number of instructions simulated
|
||||
sim_seconds 0.000008 # Number of seconds simulated
|
||||
@@ -11,8 +11,24 @@ sim_ticks 7618500 # Nu
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 15238 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.num_busy_cycles 15238 # Number of busy cycles
|
||||
system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls
|
||||
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
|
||||
system.cpu.num_fp_insts 0 # number of float instructions
|
||||
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu.num_func_calls 0 # number of times a function call or return occured
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_insts 15175 # Number of instructions executed
|
||||
system.cpu.num_refs 3684 # Number of memory references
|
||||
system.cpu.num_int_alu_accesses 12231 # Number of integer alu accesses
|
||||
system.cpu.num_int_insts 12231 # number of integer instructions
|
||||
system.cpu.num_int_register_reads 29059 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 13832 # number of times the integer registers were written
|
||||
system.cpu.num_load_insts 2232 # Number of load instructions
|
||||
system.cpu.num_mem_refs 3684 # number of memory refs
|
||||
system.cpu.num_store_insts 1452 # Number of store instructions
|
||||
system.cpu.workload.PROG:num_syscalls 18 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
||||
@@ -1,13 +1,22 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
dummy=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
mem_mode=atomic
|
||||
physmem=system.physmem
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
|
||||
@@ -1,5 +1,3 @@
|
||||
Redirecting stdout to build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/simple-timing/simout
|
||||
Redirecting stderr to build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/simple-timing/simerr
|
||||
M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2008
|
||||
@@ -7,11 +5,11 @@ The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Aug 26 2010 13:03:41
|
||||
M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
|
||||
M5 started Aug 26 2010 13:03:44
|
||||
M5 executing on zizzer
|
||||
command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/simple-timing
|
||||
M5 compiled Feb 7 2011 02:13:30
|
||||
M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
|
||||
M5 started Feb 7 2011 02:13:38
|
||||
M5 executing on burrito
|
||||
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Begining test of difficult SPARC instructions...
|
||||
|
||||
@@ -1,9 +1,9 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 255958 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 207264 # Number of bytes of host memory used
|
||||
host_seconds 0.06 # Real time elapsed on the host
|
||||
host_tick_rate 701295215 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 286147 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 223356 # Number of bytes of host memory used
|
||||
host_seconds 0.05 # Real time elapsed on the host
|
||||
host_tick_rate 784088172 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 15175 # Number of instructions simulated
|
||||
sim_seconds 0.000042 # Number of seconds simulated
|
||||
@@ -197,8 +197,24 @@ system.cpu.l2cache.warmup_cycle 0 # Cy
|
||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 83600 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.num_busy_cycles 83600 # Number of busy cycles
|
||||
system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls
|
||||
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
|
||||
system.cpu.num_fp_insts 0 # number of float instructions
|
||||
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu.num_func_calls 0 # number of times a function call or return occured
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_insts 15175 # Number of instructions executed
|
||||
system.cpu.num_refs 3684 # Number of memory references
|
||||
system.cpu.num_int_alu_accesses 12231 # Number of integer alu accesses
|
||||
system.cpu.num_int_insts 12231 # number of integer instructions
|
||||
system.cpu.num_int_register_reads 29059 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 13831 # number of times the integer registers were written
|
||||
system.cpu.num_load_insts 2232 # Number of load instructions
|
||||
system.cpu.num_mem_refs 3684 # number of memory refs
|
||||
system.cpu.num_store_insts 1452 # Number of store instructions
|
||||
system.cpu.workload.PROG:num_syscalls 18 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
||||
@@ -1,24 +1,33 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
dummy=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=LinuxAlphaSystem
|
||||
children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
|
||||
boot_cpu_frequency=500
|
||||
boot_osflags=root=/dev/hda1 console=ttyS0
|
||||
console=/chips/pd/randd/dist/binaries/console
|
||||
console=/dist/m5/system/binaries/console
|
||||
init_param=0
|
||||
kernel=/chips/pd/randd/dist/binaries/vmlinux
|
||||
kernel=/dist/m5/system/binaries/vmlinux
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=atomic
|
||||
pal=/chips/pd/randd/dist/binaries/ts_osfpal
|
||||
pal=/dist/m5/system/binaries/ts_osfpal
|
||||
physmem=system.physmem
|
||||
readfile=tests/halt.sh
|
||||
symbolfile=
|
||||
system_rev=1024
|
||||
system_type=34
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
|
||||
[system.bridge]
|
||||
type=Bridge
|
||||
@@ -265,7 +274,7 @@ table_size=65536
|
||||
|
||||
[system.disk0.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/chips/pd/randd/dist/disks/linux-latest.img
|
||||
image_file=/dist/m5/system/disks/linux-latest.img
|
||||
read_only=true
|
||||
|
||||
[system.disk2]
|
||||
@@ -285,7 +294,7 @@ table_size=65536
|
||||
|
||||
[system.disk2.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/chips/pd/randd/dist/disks/linux-bigswap2.img
|
||||
image_file=/dist/m5/system/disks/linux-bigswap2.img
|
||||
read_only=true
|
||||
|
||||
[system.intrctrl]
|
||||
@@ -411,7 +420,7 @@ system=system
|
||||
|
||||
[system.simple_disk.disk]
|
||||
type=RawDiskImage
|
||||
image_file=/chips/pd/randd/dist/disks/linux-latest.img
|
||||
image_file=/dist/m5/system/disks/linux-latest.img
|
||||
read_only=true
|
||||
|
||||
[system.terminal]
|
||||
@@ -882,7 +891,9 @@ SubsystemID=0
|
||||
SubsystemVendorID=0
|
||||
VendorID=32902
|
||||
config_latency=20000
|
||||
ctrl_offset=0
|
||||
disks=system.disk0 system.disk2
|
||||
io_shift=0
|
||||
max_backoff_delay=10000000
|
||||
min_backoff_delay=4000
|
||||
pci_bus=0
|
||||
|
||||
@@ -2,4 +2,8 @@ warn: Sockets disabled, not accepting terminal connections
|
||||
For more information see: http://www.m5sim.org/warn/8742226b
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
For more information see: http://www.m5sim.org/warn/d946bea6
|
||||
warn: Prefetch instrutions is Alpha do not do anything
|
||||
For more information see: http://www.m5sim.org/warn/3e0eccba
|
||||
warn: Prefetch instrutions is Alpha do not do anything
|
||||
For more information see: http://www.m5sim.org/warn/3e0eccba
|
||||
hack: be nice to actually delete the event here
|
||||
|
||||
@@ -1,5 +1,3 @@
|
||||
Redirecting stdout to build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual/simout
|
||||
Redirecting stderr to build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual/simerr
|
||||
M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2008
|
||||
@@ -7,13 +5,13 @@ The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Nov 2 2010 23:00:12
|
||||
M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip
|
||||
M5 started Nov 2 2010 23:09:56
|
||||
M5 executing on aus-bc2-b15
|
||||
M5 compiled Feb 7 2011 01:46:17
|
||||
M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
|
||||
M5 started Feb 7 2011 01:46:32
|
||||
M5 executing on burrito
|
||||
command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re tests/run.py build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux
|
||||
info: kernel located at: /dist/m5/system/binaries/vmlinux
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Launching CPU 1 @ 97861500
|
||||
Exiting @ tick 1870335522500 because m5_exit instruction encountered
|
||||
|
||||
@@ -1,9 +1,9 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 4418519 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 326752 # Number of bytes of host memory used
|
||||
host_seconds 14.29 # Real time elapsed on the host
|
||||
host_tick_rate 130854140423 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 1669061 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 312244 # Number of bytes of host memory used
|
||||
host_seconds 37.84 # Real time elapsed on the host
|
||||
host_tick_rate 49429698361 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 63154034 # Number of instructions simulated
|
||||
sim_seconds 1.870336 # Number of seconds simulated
|
||||
@@ -305,8 +305,24 @@ system.cpu0.kern.syscall::147 2 0.88% 100.00% # nu
|
||||
system.cpu0.kern.syscall::total 226 # number of syscalls executed
|
||||
system.cpu0.not_idle_fraction 0.015300 # Percentage of non-idle cycles
|
||||
system.cpu0.numCycles 3740670933 # number of cpu cycles simulated
|
||||
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu0.num_busy_cycles 57233843.686322 # Number of busy cycles
|
||||
system.cpu0.num_conditional_control_insts 6808233 # number of instructions that are conditional controls
|
||||
system.cpu0.num_fp_alu_accesses 299810 # Number of float alu accesses
|
||||
system.cpu0.num_fp_insts 299810 # number of float instructions
|
||||
system.cpu0.num_fp_register_reads 147724 # number of times the floating registers were read
|
||||
system.cpu0.num_fp_register_writes 150835 # number of times the floating registers were written
|
||||
system.cpu0.num_func_calls 1399585 # number of times a function call or return occured
|
||||
system.cpu0.num_idle_cycles 3683437089.313678 # Number of idle cycles
|
||||
system.cpu0.num_insts 57222076 # Number of instructions executed
|
||||
system.cpu0.num_refs 15135515 # Number of memory references
|
||||
system.cpu0.num_int_alu_accesses 53249924 # Number of integer alu accesses
|
||||
system.cpu0.num_int_insts 53249924 # number of integer instructions
|
||||
system.cpu0.num_int_register_reads 73318596 # number of times the integer registers were read
|
||||
system.cpu0.num_int_register_writes 39827534 # number of times the integer registers were written
|
||||
system.cpu0.num_load_insts 9184477 # Number of load instructions
|
||||
system.cpu0.num_mem_refs 15135515 # number of memory refs
|
||||
system.cpu0.num_store_insts 5951038 # Number of store instructions
|
||||
system.cpu1.dcache.LoadLockedReq_accesses::0 16418 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu1.dcache.LoadLockedReq_accesses::total 16418 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu1.dcache.LoadLockedReq_hits::0 15129 # number of LoadLockedReq hits
|
||||
@@ -587,8 +603,24 @@ system.cpu1.kern.syscall::132 2 2.00% 100.00% # nu
|
||||
system.cpu1.kern.syscall::total 100 # number of syscalls executed
|
||||
system.cpu1.not_idle_fraction 0.001587 # Percentage of non-idle cycles
|
||||
system.cpu1.numCycles 3740248881 # number of cpu cycles simulated
|
||||
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu1.num_busy_cycles 5936690.922345 # Number of busy cycles
|
||||
system.cpu1.num_conditional_control_insts 577190 # number of instructions that are conditional controls
|
||||
system.cpu1.num_fp_alu_accesses 28590 # Number of float alu accesses
|
||||
system.cpu1.num_fp_insts 28590 # number of float instructions
|
||||
system.cpu1.num_fp_register_reads 17889 # number of times the floating registers were read
|
||||
system.cpu1.num_fp_register_writes 17683 # number of times the floating registers were written
|
||||
system.cpu1.num_func_calls 182742 # number of times a function call or return occured
|
||||
system.cpu1.num_idle_cycles 3734312190.077655 # Number of idle cycles
|
||||
system.cpu1.num_insts 5931958 # Number of instructions executed
|
||||
system.cpu1.num_refs 1926244 # Number of memory references
|
||||
system.cpu1.num_int_alu_accesses 5550578 # Number of integer alu accesses
|
||||
system.cpu1.num_int_insts 5550578 # number of integer instructions
|
||||
system.cpu1.num_int_register_reads 7657288 # number of times the integer registers were read
|
||||
system.cpu1.num_int_register_writes 4163275 # number of times the integer registers were written
|
||||
system.cpu1.num_load_insts 1170888 # Number of load instructions
|
||||
system.cpu1.num_mem_refs 1926244 # number of memory refs
|
||||
system.cpu1.num_store_insts 755356 # Number of store instructions
|
||||
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
|
||||
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
||||
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user