DMA: Add IOCache and fix bus bridge to optionally only send requests one

way so a cache can handle partial block requests for i/o devices.

--HG--
extra : convert_revision : a68b5ae826731bc87ed93eb7ef326a2393053964

src/mem/cache/base_cache.cc

@@ -40,9 +40,10 @@
 
 using namespace std;
 
-BaseCache::CachePort::CachePort(const std::string &_name, BaseCache *_cache)
+BaseCache::CachePort::CachePort(const std::string &_name, BaseCache *_cache,
+        std::vector<Range<Addr> > filter_ranges)
     : SimpleTimingPort(_name, _cache), cache(_cache), otherPort(NULL),
-      blocked(false), mustSendRetry(false)
+      blocked(false), mustSendRetry(false), filterRanges(filter_ranges)
 {
 }