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DMA: Add IOCache and fix bus bridge to optionally only send requests one

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way so a cache can handle partial block requests for i/o devices.

--HG--
extra : convert_revision : a68b5ae826731bc87ed93eb7ef326a2393053964
This commit is contained in:
Ali Saidi
2007-08-10 16:14:01 -04:00
parent 5c38668ed6
commit 06a9f58c68
16 changed files with 134 additions and 49 deletions
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4
src/mem/cache/BaseCache.py vendored
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@@ -81,4 +81,8 @@ class BaseCache(MemObject):
"Only prefetch on data not on instruction accesses")
cpu_side = Port("Port on side closer to CPU")
mem_side = Port("Port on side closer to MEM")
cpu_side_filter_ranges = VectorParam.AddrRange([],
"What addresses shouldn't be passed through the side of the bridge")
mem_side_filter_ranges = VectorParam.AddrRange([],
"What addresses shouldn't be passed through the side of the bridge")
addr_range = VectorParam.AddrRange(AllMemory, "The address range in bytes")