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fastmodel: Move the ARM IRIS threadcontext into CortexA76.

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This specialization will correspond specifically with the CortexA76,
instead of specializing the ThreadContext for ARM in general. Some
aspects of this class may need to move into the base IRIS thread
context class, but I'll leave that for a later change.

Change-Id: I9cbe527d36e6fda78601dc39c1963370cfa28b16
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23787
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2019-11-05 16:35:29 -08:00
parent 2093d84a77
commit 062686655e
5 changed files with 40 additions and 72 deletions
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1
src/arch/arm/fastmodel/CortexA76/SConscript
View File

@@ -42,3 +42,4 @@ for name in ('x1', 'x2', 'x3', 'x4'):
SimObject('FastModelCortexA76.py')
Source('cortex_a76.cc')
Source('evs.cc')
Source('thread_context.cc')

6
src/arch/arm/fastmodel/CortexA76/cortex_a76.hh
View File

@@ -30,8 +30,8 @@
#ifndef __ARCH_ARM_FASTMODEL_CORTEXA76_CORETEX_A76_HH__
#define __ARCH_ARM_FASTMODEL_CORTEXA76_CORETEX_A76_HH__
#include "arch/arm/fastmodel/CortexA76/thread_context.hh"
#include "arch/arm/fastmodel/amba_ports.hh"
#include "arch/arm/fastmodel/iris/arm/thread_context.hh"
#include "arch/arm/fastmodel/iris/cpu.hh"
#include "params/FastModelCortexA76.hh"
#include "params/FastModelCortexA76Cluster.hh"
@@ -51,11 +51,11 @@ namespace FastModel
// the work.
class CortexA76Cluster;
class CortexA76 : public Iris::CPU<Iris::ArmThreadContext>
class CortexA76 : public Iris::CPU<CortexA76TC>
{
protected:
typedef FastModelCortexA76Params Params;
typedef Iris::CPU<Iris::ArmThreadContext> Base;
typedef Iris::CPU<CortexA76TC> Base;
const Params &_params;
CortexA76Cluster *cluster = nullptr;

52
src/arch/arm/fastmodel/iris/arm/thread_context.cc → src/arch/arm/fastmodel/CortexA76/thread_context.cc
View File

@@ -27,16 +27,16 @@
* Authors: Gabe Black
*/
#include "arch/arm/fastmodel/iris/arm/thread_context.hh"
#include "arch/arm/fastmodel/CortexA76/thread_context.hh"
#include "arch/arm/fastmodel/iris/memory_spaces.hh"
#include "iris/detail/IrisCppAdapter.h"
#include "iris/detail/IrisObjects.h"
namespace Iris
namespace FastModel
{
ArmThreadContext::ArmThreadContext(
CortexA76TC::CortexA76TC(
::BaseCPU *cpu, int id, System *system, ::BaseTLB *dtb, ::BaseTLB *itb,
iris::IrisConnectionInterface *iris_if,
const std::string &iris_path) :
@@ -45,24 +45,24 @@ ArmThreadContext::ArmThreadContext(
{}
bool
ArmThreadContext::translateAddress(Addr &paddr, Addr vaddr)
CortexA76TC::translateAddress(Addr &paddr, Addr vaddr)
{
// Determine what memory spaces are currently active.
CanonicalMsn in_msn;
Iris::CanonicalMsn in_msn;
switch (currEL(this)) {
case EL3:
in_msn = SecureMonitorMsn;
in_msn = Iris::SecureMonitorMsn;
break;
case EL2:
in_msn = NsHypMsn;
in_msn = Iris::NsHypMsn;
break;
default:
in_msn = GuestMsn;
in_msn = Iris::GuestMsn;
break;
}
CanonicalMsn out_msn = inSecureState(this) ?
PhysicalMemorySecureMsn : PhysicalMemoryNonSecureMsn;
Iris::CanonicalMsn out_msn = inSecureState(this) ?
Iris::PhysicalMemorySecureMsn : Iris::PhysicalMemoryNonSecureMsn;
// Figure out what memory spaces match the canonical numbers we need.
iris::MemorySpaceId in = iris::IRIS_UINT64_MAX;
@@ -82,7 +82,7 @@ ArmThreadContext::translateAddress(Addr &paddr, Addr vaddr)
}
void
ArmThreadContext::initFromIrisInstance(const ResourceMap &resources)
CortexA76TC::initFromIrisInstance(const ResourceMap &resources)
{
ThreadContext::initFromIrisInstance(resources);
@@ -98,7 +98,7 @@ ArmThreadContext::initFromIrisInstance(const ResourceMap &resources)
}
TheISA::PCState
ArmThreadContext::pcState() const
CortexA76TC::pcState() const
{
ArmISA::CPSR cpsr = readMiscRegNoEffect(ArmISA::MISCREG_CPSR);
ArmISA::PCState pc;
@@ -121,7 +121,7 @@ ArmThreadContext::pcState() const
return pc;
}
void
ArmThreadContext::pcState(const TheISA::PCState &val)
CortexA76TC::pcState(const TheISA::PCState &val)
{
Addr pc = val.pc();
@@ -134,19 +134,19 @@ ArmThreadContext::pcState(const TheISA::PCState &val)
}
Addr
ArmThreadContext::instAddr() const
CortexA76TC::instAddr() const
{
return pcState().instAddr();
}
Addr
ArmThreadContext::nextInstAddr() const
CortexA76TC::nextInstAddr() const
{
return pcState().nextInstAddr();
}
iris::MemorySpaceId
ArmThreadContext::getBpSpaceId(Addr pc) const
CortexA76TC::getBpSpaceId(Addr pc) const
{
if (bpSpaceId == iris::IRIS_UINT64_MAX) {
for (auto &space: memorySpaces) {
@@ -162,7 +162,7 @@ ArmThreadContext::getBpSpaceId(Addr pc) const
}
uint64_t
ArmThreadContext::readIntReg(RegIndex reg_idx) const
CortexA76TC::readIntReg(RegIndex reg_idx) const
{
ArmISA::CPSR cpsr = readMiscRegNoEffect(ArmISA::MISCREG_CPSR);
@@ -175,7 +175,7 @@ ArmThreadContext::readIntReg(RegIndex reg_idx) const
}
void
ArmThreadContext::setIntReg(RegIndex reg_idx, uint64_t val)
CortexA76TC::setIntReg(RegIndex reg_idx, uint64_t val)
{
ArmISA::CPSR cpsr = readMiscRegNoEffect(ArmISA::MISCREG_CPSR);
@@ -187,7 +187,7 @@ ArmThreadContext::setIntReg(RegIndex reg_idx, uint64_t val)
}
const ArmISA::VecRegContainer &
ArmThreadContext::readVecReg(const RegId &reg_id) const
CortexA76TC::readVecReg(const RegId &reg_id) const
{
const RegIndex idx = reg_id.index();
// Ignore accesses to registers which aren't architected. gem5 defines a
@@ -207,12 +207,12 @@ ArmThreadContext::readVecReg(const RegId &reg_id) const
}
const ArmISA::VecRegContainer &
ArmThreadContext::readVecRegFlat(RegIndex idx) const
CortexA76TC::readVecRegFlat(RegIndex idx) const
{
return readVecReg(RegId(VecRegClass, idx));
}
Iris::ThreadContext::IdxNameMap ArmThreadContext::miscRegIdxNameMap({
Iris::ThreadContext::IdxNameMap CortexA76TC::miscRegIdxNameMap({
{ ArmISA::MISCREG_CPSR, "CPSR" },
{ ArmISA::MISCREG_SPSR, "SPSR" },
{ ArmISA::MISCREG_SPSR_FIQ, "SPSR_fiq" },
@@ -844,7 +844,7 @@ Iris::ThreadContext::IdxNameMap ArmThreadContext::miscRegIdxNameMap({
{ ArmISA::MISCREG_VDISR_EL2, "VDISR_EL2" }
});
Iris::ThreadContext::IdxNameMap ArmThreadContext::intReg32IdxNameMap({
Iris::ThreadContext::IdxNameMap CortexA76TC::intReg32IdxNameMap({
{ ArmISA::INTREG_R0, "R0" },
{ ArmISA::INTREG_R1, "R1" },
{ ArmISA::INTREG_R2, "R2" },
@@ -863,7 +863,7 @@ Iris::ThreadContext::IdxNameMap ArmThreadContext::intReg32IdxNameMap({
{ ArmISA::INTREG_R15, "R15" }
});
Iris::ThreadContext::IdxNameMap ArmThreadContext::intReg64IdxNameMap({
Iris::ThreadContext::IdxNameMap CortexA76TC::intReg64IdxNameMap({
{ ArmISA::INTREG_X0, "X0" },
{ ArmISA::INTREG_X1, "X1" },
{ ArmISA::INTREG_X2, "X2" },
@@ -898,7 +898,7 @@ Iris::ThreadContext::IdxNameMap ArmThreadContext::intReg64IdxNameMap({
{ ArmISA::INTREG_SPX, "SP" },
});
Iris::ThreadContext::IdxNameMap ArmThreadContext::vecRegIdxNameMap({
Iris::ThreadContext::IdxNameMap CortexA76TC::vecRegIdxNameMap({
{ 0, "V0" }, { 1, "V1" }, { 2, "V2" }, { 3, "V3" },
{ 4, "V4" }, { 5, "V5" }, { 6, "V6" }, { 7, "V7" },
{ 8, "V8" }, { 9, "V9" }, { 10, "V10" }, { 11, "V11" },
@@ -909,6 +909,6 @@ Iris::ThreadContext::IdxNameMap ArmThreadContext::vecRegIdxNameMap({
{ 28, "V28" }, { 29, "V29" }, { 30, "V30" }, { 31, "V31" }
});
iris::MemorySpaceId ArmThreadContext::bpSpaceId = iris::IRIS_UINT64_MAX;
iris::MemorySpaceId CortexA76TC::bpSpaceId = iris::IRIS_UINT64_MAX;
} // namespace Iris
} // namespace FastModel

20
src/arch/arm/fastmodel/iris/arm/thread_context.hh → src/arch/arm/fastmodel/CortexA76/thread_context.hh
View File

@@ -27,17 +27,17 @@
* Authors: Gabe Black
*/
#ifndef __ARCH_ARM_FASTMODEL_IRIS_ARM_THREAD_CONTEXT_HH__
#define __ARCH_ARM_FASTMODEL_IRIS_ARM_THREAD_CONTEXT_HH__
#ifndef __ARCH_ARM_FASTMODEL_CORTEXA76_THREAD_CONTEXT_HH__
#define __ARCH_ARM_FASTMODEL_CORTEXA76_THREAD_CONTEXT_HH__
#include "arch/arm/fastmodel/iris/thread_context.hh"
namespace Iris
namespace FastModel
{
// This ThreadContext class translates accesses to state using gem5's native
// to the Iris API. This includes extracting and translating register indices.
class ArmThreadContext : public Iris::ThreadContext
class CortexA76TC : public Iris::ThreadContext
{
protected:
static IdxNameMap miscRegIdxNameMap;
@@ -51,10 +51,10 @@ class ArmThreadContext : public Iris::ThreadContext
mutable std::vector<ArmISA::VecRegContainer> vecRegs;
public:
ArmThreadContext(::BaseCPU *cpu, int id, System *system,
::BaseTLB *dtb, ::BaseTLB *itb,
iris::IrisConnectionInterface *iris_if,
const std::string &iris_path);
CortexA76TC(::BaseCPU *cpu, int id, System *system,
::BaseTLB *dtb, ::BaseTLB *itb,
iris::IrisConnectionInterface *iris_if,
const std::string &iris_path);
bool translateAddress(Addr &paddr, Addr vaddr) override;
@@ -86,6 +86,6 @@ class ArmThreadContext : public Iris::ThreadContext
const VecRegContainer &readVecRegFlat(RegIndex idx) const override;
};
} // namespace Iris
} // namespace FastModel
#endif // __ARCH_ARM_FASTMODEL_IRIS_ARM_THREAD_CONTEXT_HH__
#endif // __ARCH_ARM_FASTMODEL_CORTEXA76_THREAD_CONTEXT_HH__

33
src/arch/arm/fastmodel/iris/arm/SConscript
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@@ -1,33 +0,0 @@
# Copyright 2019 Google, Inc.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Gabe Black
Import('*')
if not env['USE_ARM_FASTMODEL'] or env['TARGET_ISA'] != 'arm':
Return()
Source('thread_context.cc')