From ebef2fc4b142a4dac911a76f499c80fead842e47 Mon Sep 17 00:00:00 2001 From: Giacomo Travaglini Date: Fri, 2 Feb 2024 08:55:48 +0000 Subject: [PATCH 1/2] arch-arm: Crypto instructions checking release object Check directly if extension is enabled instead of looking for ID register field value. This makes the code more readable Change-Id: If0b882ac3464c3587731b72a7edb3b8b65ea86c7 Signed-off-by: Giacomo Travaglini Reviewed-by: Andreas Sandberg --- src/arch/arm/isa/insts/crypto.isa | 17 +++++++++++------ src/arch/arm/isa/insts/crypto64.isa | 17 +++++++++++------ 2 files changed, 22 insertions(+), 12 deletions(-) diff --git a/src/arch/arm/isa/insts/crypto.isa b/src/arch/arm/isa/insts/crypto.isa index b6c3ad3c20..bbefa055e0 100644 --- a/src/arch/arm/isa/insts/crypto.isa +++ b/src/arch/arm/isa/insts/crypto.isa @@ -1,6 +1,6 @@ // -*- mode:c++ -*- // -// Copyright (c) 2018 ARM Limited +// Copyright (c) 2018, 2024 Arm Limited // All rights reserved // // The license below extends only to copyright in the software and shall @@ -38,8 +38,7 @@ let {{ cryptoEnabledCheckCode = ''' - auto crypto_reg = xc->tcBase()->readMiscReg(MISCREG_ID_ISAR5); - if (!(crypto_reg & %(mask)d)) { + if (!HaveExt(xc->tcBase(), %(extension)s)) { return std::make_shared(machInst, true); } ''' @@ -150,7 +149,9 @@ let {{ sha256_su0Code = "crypto.sha256Su0(output, input);" sha256_su1Code = "crypto.sha256Su1(output, input, input2);" - aes_enabled = cryptoEnabledCheckCode % { "mask" : 0xF0 } + aes_enabled = cryptoEnabledCheckCode % { + "extension" : "ArmExtension::FEAT_AES" + } cryptoRegRegRegInst("aese", "AESE", "SimdAesOp", aes_enabled, aeseCode) cryptoRegRegRegInst("aesd", "AESD", "SimdAesOp", @@ -160,7 +161,9 @@ let {{ cryptoRegRegInst("aesimc", "AESIMC", "SimdAesMixOp", aes_enabled, aesimcCode) - sha1_enabled = cryptoEnabledCheckCode % { "mask" : 0xF00 } + sha1_enabled = cryptoEnabledCheckCode % { + "extension" : "ArmExtension::FEAT_SHA1" + } cryptoRegRegRegInst("sha1c", "SHA1C", "SimdSha1HashOp", sha1_enabled, sha1_cCode) cryptoRegRegRegInst("sha1p", "SHA1P", "SimdSha1HashOp", @@ -174,7 +177,9 @@ let {{ cryptoRegRegInst("sha1su1", "SHA1SU1", "SimdShaSigma2Op", sha1_enabled, sha1_su1Code) - sha2_enabled = cryptoEnabledCheckCode % { "mask" : 0xF000 } + sha2_enabled = cryptoEnabledCheckCode % { + "extension" : "ArmExtension::FEAT_SHA256" + } cryptoRegRegRegInst("sha256h", "SHA256H", "SimdSha256HashOp", sha2_enabled, sha256_hCode) cryptoRegRegRegInst("sha256h2", "SHA256H2", "SimdSha256Hash2Op", diff --git a/src/arch/arm/isa/insts/crypto64.isa b/src/arch/arm/isa/insts/crypto64.isa index 1ae580fa97..a96789d9ec 100644 --- a/src/arch/arm/isa/insts/crypto64.isa +++ b/src/arch/arm/isa/insts/crypto64.isa @@ -1,6 +1,6 @@ // -*- mode:c++ -*- // -// Copyright (c) 2018 ARM Limited +// Copyright (c) 2018, 2024 Arm Limited // All rights reserved // // The license below extends only to copyright in the software and shall @@ -41,8 +41,7 @@ let {{ exec_output = "" cryptoEnabledCheckCode = ''' - auto crypto_reg = xc->tcBase()->readMiscReg(MISCREG_ID_AA64ISAR0_EL1); - if (!(crypto_reg & %(mask)d)) { + if (!HaveExt(xc->tcBase(), %(extension)s)) { return std::make_shared(machInst, true); } ''' @@ -133,7 +132,9 @@ let {{ sha256_su0Code = "crypto.sha256Su0(output, input);" sha256_su1Code = "crypto.sha256Su1(output, input, input2);" - aes_enabled = cryptoEnabledCheckCode % { "mask" : 0xF0 } + aes_enabled = cryptoEnabledCheckCode % { + "extension" : "ArmExtension::FEAT_AES" + } cryptoRegRegRegInst("aese", "AESE64", "SimdAesOp", aes_enabled, aeseCode) cryptoRegRegRegInst("aesd", "AESD64", "SimdAesOp", @@ -143,7 +144,9 @@ let {{ cryptoRegRegInst("aesimc", "AESIMC64", "SimdAesMixOp", aes_enabled, aesimcCode) - sha1_enabled = cryptoEnabledCheckCode % { "mask" : 0xF00 } + sha1_enabled = cryptoEnabledCheckCode % { + "extension" : "ArmExtension::FEAT_SHA1" + } cryptoRegRegRegInst("sha1c", "SHA1C64", "SimdSha1HashOp", sha1_enabled, sha1_cCode) cryptoRegRegRegInst("sha1p", "SHA1P64", "SimdSha1HashOp", @@ -157,7 +160,9 @@ let {{ cryptoRegRegInst("sha1su1", "SHA1SU164", "SimdShaSigma2Op", sha1_enabled, sha1_su1Code) - sha2_enabled = cryptoEnabledCheckCode % { "mask" : 0xF000 } + sha2_enabled = cryptoEnabledCheckCode % { + "extension" : "ArmExtension::FEAT_SHA256" + } cryptoRegRegRegInst("sha256h", "SHA256H64", "SimdSha256HashOp", sha2_enabled, sha256_hCode) cryptoRegRegRegInst("sha256h2", "SHA256H264", "SimdSha256Hash2Op", From 16e06bad0c94964cdde99b783d84162ec54c4fc1 Mon Sep 17 00:00:00 2001 From: Giacomo Travaglini Date: Fri, 2 Feb 2024 09:27:09 +0000 Subject: [PATCH 2/2] arch-arm: Exec Crypto instructions only if SIMD&FP enabled We not only check for the presence of the relative FEAT_*, we also check if AdvSIMD is enabled; we throw an undefined instruction otherwise. Change-Id: I1fd0cdc8057c5a7901774802dc076817f06c8e66 Signed-off-by: Giacomo Travaglini Reviewed-by: Andreas Sandberg --- src/arch/arm/isa/insts/crypto.isa | 2 +- src/arch/arm/isa/insts/crypto64.isa | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/src/arch/arm/isa/insts/crypto.isa b/src/arch/arm/isa/insts/crypto.isa index bbefa055e0..5faa4b90d5 100644 --- a/src/arch/arm/isa/insts/crypto.isa +++ b/src/arch/arm/isa/insts/crypto.isa @@ -41,7 +41,7 @@ let {{ if (!HaveExt(xc->tcBase(), %(extension)s)) { return std::make_shared(machInst, true); } - ''' + ''' + simdEnabledCheckCode header_output = "" decoder_output = "" diff --git a/src/arch/arm/isa/insts/crypto64.isa b/src/arch/arm/isa/insts/crypto64.isa index a96789d9ec..0ed0867136 100644 --- a/src/arch/arm/isa/insts/crypto64.isa +++ b/src/arch/arm/isa/insts/crypto64.isa @@ -44,7 +44,8 @@ let {{ if (!HaveExt(xc->tcBase(), %(extension)s)) { return std::make_shared(machInst, true); } - ''' + ''' + simd64EnabledCheckCode + cryptoRegRegRegPrefix = ''' Crypto crypto; RegVect srcReg1, srcReg2, destReg;