From 05866c82f9eb80db05fb423addcc8563efe1b744 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Fri, 13 May 2011 17:27:02 -0500 Subject: [PATCH] ARM: Construct the predicate test register for more instruction programatically. If one of the condition codes isn't being used in the execution we should only read it if the instruction might be dependent on it. With the preeceding changes there are several more cases where we should dynamically pick instead of assuming as we did before. --- src/arch/arm/isa/formats/pred.isa | 32 +++++++++---------- src/arch/arm/isa/insts/data.isa | 48 +++++++++++++---------------- src/arch/arm/isa/insts/ldr.isa | 2 +- src/arch/arm/isa/insts/macromem.isa | 27 +++++++--------- src/arch/arm/isa/insts/mem.isa | 25 ++++++++++----- src/arch/arm/isa/insts/misc.isa | 8 ++--- src/arch/arm/isa/insts/mult.isa | 12 ++++---- src/arch/arm/isa/insts/str.isa | 2 +- src/arch/arm/isa/operands.isa | 5 +++ 9 files changed, 83 insertions(+), 78 deletions(-) diff --git a/src/arch/arm/isa/formats/pred.isa b/src/arch/arm/isa/formats/pred.isa index bd6ccddd10..b9745e8baa 100644 --- a/src/arch/arm/isa/formats/pred.isa +++ b/src/arch/arm/isa/formats/pred.isa @@ -48,10 +48,10 @@ let {{ CpsrQ = (Rd < resTemp) ? 1 << 27 : 0; } else { uint16_t _ic, _iv, _iz, _in; - _in = (resTemp >> %(negBit)d) & 1; + _in = (resTemp >> %(negBit)d); _iz = (resTemp == 0); - _iv = %(ivValue)s & 1; - _ic = %(icValue)s & 1; + _iv = %(ivValue)s; + _ic = %(icValue)s; CondCodesNZ = (_in << 1) | (_iz); CondCodesC = _ic; @@ -138,23 +138,23 @@ let {{ def format DataOp(code, flagtype = logic) {{ (regCcCode, immCcCode) = getCcCode(flagtype) regCode = '''uint32_t op2 = shift_rm_rs(Rm, Rs<7:0>, - shift, CondCodesC); + shift, 0); op2 = op2;''' + code immCode = '''uint32_t op2 = shift_rm_imm(Rm, shift_size, - shift, CondCodesC); + shift, OptShiftRmCondCodesC); op2 = op2;''' + code regIop = InstObjParams(name, Name, 'PredIntOp', {"code": regCode, - "predicate_test": predicateTest}) + "predicate_test": pickPredicate(regCode)}) immIop = InstObjParams(name, Name + "Imm", 'PredIntOp', {"code": immCode, - "predicate_test": predicateTest}) + "predicate_test": pickPredicate(imm)}) regCcIop = InstObjParams(name, Name + "Cc", 'PredIntOp', - {"code": regCode + regCcCode, - "predicate_test": condPredicateTest}) + {"code": regCode + regCcCode, + "predicate_test": pickPredicate(regCode + regCcCode)}) immCcIop = InstObjParams(name, Name + "ImmCc", 'PredIntOp', - {"code": immCode + immCcCode, - "predicate_test": condPredicateTest}) + {"code": immCode + immCcCode, + "predicate_test": pickPredicate(immCode + immCcCode)}) header_output = BasicDeclare.subst(regIop) + \ BasicDeclare.subst(immIop) + \ BasicDeclare.subst(regCcIop) + \ @@ -174,10 +174,10 @@ def format DataImmOp(code, flagtype = logic) {{ code += "resTemp = resTemp;" iop = InstObjParams(name, Name, 'PredImmOp', {"code": code, - "predicate_test": predicateTest}) + "predicate_test": pickPredicate(code)}) ccIop = InstObjParams(name, Name + "Cc", 'PredImmOp', - {"code": code + getImmCcCode(flagtype), - "predicate_test": condPredicateTest}) + {"code": code + getImmCcCode(flagtype), + "predicate_test": pickPredicate(code + getImmCcCode(flagtype))}) header_output = BasicDeclare.subst(iop) + \ BasicDeclare.subst(ccIop) decoder_output = BasicConstructor.subst(iop) + \ @@ -190,7 +190,7 @@ def format DataImmOp(code, flagtype = logic) {{ def format PredOp(code, *opt_flags) {{ iop = InstObjParams(name, Name, 'PredOp', {"code": code, - "predicate_test": predicateTest}, + "predicate_test": pickPredicate(code)}, opt_flags) header_output = BasicDeclare.subst(iop) decoder_output = BasicConstructor.subst(iop) @@ -201,7 +201,7 @@ def format PredOp(code, *opt_flags) {{ def format PredImmOp(code, *opt_flags) {{ iop = InstObjParams(name, Name, 'PredImmOp', {"code": code, - "predicate_test": predicateTest}, + "predicate_test": pickPredicate(code)}, opt_flags) header_output = BasicDeclare.subst(iop) decoder_output = BasicConstructor.subst(iop) diff --git a/src/arch/arm/isa/insts/data.isa b/src/arch/arm/isa/insts/data.isa index 94693c8ef3..41722914a1 100644 --- a/src/arch/arm/isa/insts/data.isa +++ b/src/arch/arm/isa/insts/data.isa @@ -103,8 +103,8 @@ let {{ secondOpRe = re.compile("secondOp") immOp2 = "imm" - regOp2 = "shift_rm_imm(Op2, shiftAmt, shiftType, CondCodesC)" - regRegOp2 = "shift_rm_rs(Op2, Shift<7:0>, shiftType, CondCodesC)" + regOp2 = "shift_rm_imm(Op2, shiftAmt, shiftType, OptShiftRmCondCodesC)" + regRegOp2 = "shift_rm_rs(Op2, Shift<7:0>, shiftType, 0)" def buildImmDataInst(mnem, code, flagType = "logic", suffix = "Imm", \ buildCc = True, buildNonCc = True, instFlags = []): @@ -125,12 +125,12 @@ let {{ } immCode = secondOpRe.sub(immOp2, code) immIop = InstObjParams(mnem, mnem.capitalize() + suffix, "DataImmOp", - {"code" : immCode, - "predicate_test": predicateTest}, instFlags) + {"code" : immCode, + "predicate_test": pickPredicate(immCode)}, instFlags) immIopCc = InstObjParams(mnem + "s", mnem.capitalize() + suffix + "Cc", - "DataImmOp", - {"code" : immCode + immCcCode, - "predicate_test": condPredicateTest}, instFlags) + "DataImmOp", + {"code" : immCode + immCcCode, + "predicate_test": pickPredicate(immCode + immCcCode)}, instFlags) def subst(iop): global header_output, decoder_output, exec_output @@ -163,15 +163,15 @@ let {{ } regCode = secondOpRe.sub(regOp2, code) regIop = InstObjParams(mnem, mnem.capitalize() + suffix, "DataRegOp", - {"code" : regCode, "is_ras_pop" : isRasPop, - "is_branch" : isBranch, - "predicate_test": predicateTest}, instFlags) + {"code" : regCode, "is_ras_pop" : isRasPop, + "is_branch" : isBranch, + "predicate_test": pickPredicate(regCode)}, instFlags) regIopCc = InstObjParams(mnem + "s", mnem.capitalize() + suffix + "Cc", - "DataRegOp", - {"code" : regCode + regCcCode, - "predicate_test": condPredicateTest, - "is_ras_pop" : isRasPop, - "is_branch" : isBranch}, instFlags) + "DataRegOp", + {"code" : regCode + regCcCode, + "predicate_test": pickPredicate(regCode + regCcCode), + "is_ras_pop" : isRasPop, + "is_branch" : isBranch}, instFlags) def subst(iop): global header_output, decoder_output, exec_output @@ -204,14 +204,14 @@ let {{ } regRegCode = secondOpRe.sub(regRegOp2, code) regRegIop = InstObjParams(mnem, mnem.capitalize() + suffix, - "DataRegRegOp", - {"code" : regRegCode, - "predicate_test": predicateTest}) + "DataRegRegOp", + {"code" : regRegCode, + "predicate_test": pickPredicate(regRegCode)}) regRegIopCc = InstObjParams(mnem + "s", - mnem.capitalize() + suffix + "Cc", - "DataRegRegOp", - {"code" : regRegCode + regRegCcCode, - "predicate_test": condPredicateTest}) + mnem.capitalize() + suffix + "Cc", + "DataRegRegOp", + {"code" : regRegCode + regRegCcCode, + "predicate_test": pickPredicate(regRegCode + regRegCcCode)}) def subst(iop): global header_output, decoder_output, exec_output @@ -241,10 +241,6 @@ let {{ code += ''' SCTLR sctlr = Sctlr; CPSR old_cpsr = Cpsr; - old_cpsr.nz = CondCodesNZ; - old_cpsr.c = CondCodesC; - old_cpsr.v = CondCodesV; - old_cpsr.ge = CondCodesGE; CPSR new_cpsr = cpsrWriteByInstr(old_cpsr, Spsr, 0xF, true, sctlr.nmfi); diff --git a/src/arch/arm/isa/insts/ldr.isa b/src/arch/arm/isa/insts/ldr.isa index a346c495a8..4c8bfd6127 100644 --- a/src/arch/arm/isa/insts/ldr.isa +++ b/src/arch/arm/isa/insts/ldr.isa @@ -141,7 +141,7 @@ let {{ def __init__(self, *args, **kargs): super(LoadRegInst, self).__init__(*args, **kargs) self.offset = self.op + " shift_rm_imm(Index, shiftAmt," + \ - " shiftType, CondCodesC)" + " shiftType, OptShiftRmCondCodesC)" if self.add: self.wbDecl = ''' MicroAddUop(machInst, base, base, wbIndexReg, shiftAmt, shiftType); diff --git a/src/arch/arm/isa/insts/macromem.isa b/src/arch/arm/isa/insts/macromem.isa index 31545d3a40..d5800576c0 100644 --- a/src/arch/arm/isa/insts/macromem.isa +++ b/src/arch/arm/isa/insts/macromem.isa @@ -89,10 +89,6 @@ let {{ microRetUopCode = ''' CPSR old_cpsr = Cpsr; SCTLR sctlr = Sctlr; - old_cpsr.nz = CondCodesNZ; - old_cpsr.c = CondCodesC; - old_cpsr.v = CondCodesV; - old_cpsr.ge = CondCodesGE; CPSR new_cpsr = cpsrWriteByInstr(old_cpsr, Spsr, 0xF, true, sctlr.nmfi); @@ -588,14 +584,14 @@ let {{ 'predicate_test': predicateTest}, ['IsMicroop']) + microAddUopCode = ''' + URa = URb + shift_rm_imm(URc, shiftAmt, shiftType, OptShiftRmCondCodesC); + ''' + microAddUopIop = InstObjParams('add_uop', 'MicroAddUop', 'MicroIntRegOp', - {'code': - '''URa = URb + shift_rm_imm(URc, shiftAmt, - shiftType, - CondCodesC); - ''', - 'predicate_test': predicateTest}, + {'code': microAddUopCode, + 'predicate_test': pickPredicate(microAddUopCode)}, ['IsMicroop']) microSubiUopIop = InstObjParams('subi_uop', 'MicroSubiUop', @@ -604,14 +600,13 @@ let {{ 'predicate_test': predicateTest}, ['IsMicroop']) + microSubUopCode = ''' + URa = URb - shift_rm_imm(URc, shiftAmt, shiftType, OptShiftRmCondCodesC); + ''' microSubUopIop = InstObjParams('sub_uop', 'MicroSubUop', 'MicroIntRegOp', - {'code': - '''URa = URb - shift_rm_imm(URc, shiftAmt, - shiftType, - CondCodesC); - ''', - 'predicate_test': predicateTest}, + {'code': microSubUopCode, + 'predicate_test': pickPredicate(microSubUopCode)}, ['IsMicroop']) microUopRegMovIop = InstObjParams('uopReg_uop', 'MicroUopRegMov', diff --git a/src/arch/arm/isa/insts/mem.isa b/src/arch/arm/isa/insts/mem.isa index cad0b1589d..fb09eacb64 100644 --- a/src/arch/arm/isa/insts/mem.isa +++ b/src/arch/arm/isa/insts/mem.isa @@ -120,14 +120,21 @@ let {{ def pickPredicate(blobs): opt_nz = True - opt_c = True + opt_c = 'opt' opt_v = True - for val in blobs.values(): - if re.search('(?