CPU: Make Exec trace to print predication result (if false) for memory instructions

src/cpu/base_dyn_inst.hh

@@ -805,6 +805,10 @@ class BaseDynInst : public FastAlloc, public RefCounted
     void setPredicate(bool val)
     {
         predicate = val;
+
+        if (traceData) {
+            traceData->setPredicate(val);
+        }
     }
 
     /** Sets the ASID. */

src/cpu/exetrace.cc

@@ -111,6 +111,10 @@ Trace::ExeTracerRecord::traceInst(StaticInstPtr inst, bool ran)
             outs << Enums::OpClassStrings[inst->opClass()] << " : ";
         }
 
+        if (IsOn(ExecResult) && predicate == false) {
+            outs << "Predicated False";
+        }
+
         if (IsOn(ExecResult) && data_status != DataInvalid) {
             ccprintf(outs, " D=%#018x", data.as_int);
         }

src/cpu/o3/lsq_unit_impl.hh

@@ -458,6 +458,9 @@ LSQUnit<Impl>::executeLoad(DynInstPtr &inst)
         // realizes there is activity.
         // Mark it as executed unless it is an uncached load that
         // needs to hit the head of commit.
+        DPRINTF(LSQUnit, "Load [sn:%lli] not executed from %s\n",
+                inst->seqNum,
+                (load_fault != NoFault ? "fault" : "predication"));
         if (!(inst->hasRequest() && inst->uncacheable()) ||
             inst->isAtCommit()) {
             inst->setExecuted();

src/cpu/simple/base.hh

@@ -295,7 +295,12 @@ class BaseSimpleCPU : public BaseCPU
     void setNextMicroPC(uint64_t val) { thread->setNextMicroPC(val); }
     void setNextNPC(uint64_t val) { thread->setNextNPC(val); }
     void setPredicate(bool val)
-    { return thread->setPredicate(val); }
+    {
+        thread->setPredicate(val);
+        if (traceData) {
+            traceData->setPredicate(val);
+        }
+    }
 
     MiscReg readMiscRegNoEffect(int misc_reg)
     {