diff --git a/src/cpu/o3/scoreboard.hh b/src/cpu/o3/scoreboard.hh index 239497aa55..85a70d94b2 100644 --- a/src/cpu/o3/scoreboard.hh +++ b/src/cpu/o3/scoreboard.hh @@ -58,7 +58,7 @@ class Scoreboard std::vector regScoreBoard; /** The number of actual physical registers */ - M5_CLASS_VAR_USED unsigned numPhysRegs; + GEM5_CLASS_VAR_USED unsigned numPhysRegs; public: /** Constructs a scoreboard. diff --git a/src/dev/arm/smmu_v3_transl.hh b/src/dev/arm/smmu_v3_transl.hh index bfe6319d36..fbe97b01e9 100644 --- a/src/dev/arm/smmu_v3_transl.hh +++ b/src/dev/arm/smmu_v3_transl.hh @@ -97,7 +97,7 @@ class SMMUTranslationProcess : public SMMUProcess TranslContext context; Tick recvTick; - M5_CLASS_VAR_USED Tick faultTick; + GEM5_CLASS_VAR_USED Tick faultTick; virtual void main(Yield &yield); diff --git a/src/mem/mem_interface.hh b/src/mem/mem_interface.hh index d1bf671e88..7710e95bfb 100644 --- a/src/mem/mem_interface.hh +++ b/src/mem/mem_interface.hh @@ -140,7 +140,7 @@ class MemInterface : public AbstractMemory /** * General timing requirements */ - M5_CLASS_VAR_USED const Tick tCK; + GEM5_CLASS_VAR_USED const Tick tCK; const Tick tCS; const Tick tBURST; const Tick tRTW; diff --git a/src/mem/ruby/network/garnet/OutputUnit.hh b/src/mem/ruby/network/garnet/OutputUnit.hh index 12452691a6..fe7f889526 100644 --- a/src/mem/ruby/network/garnet/OutputUnit.hh +++ b/src/mem/ruby/network/garnet/OutputUnit.hh @@ -99,7 +99,7 @@ class OutputUnit : public Consumer private: Router *m_router; - M5_CLASS_VAR_USED int m_id; + GEM5_CLASS_VAR_USED int m_id; PortDirection m_direction; int m_vc_per_vnet; NetworkLink *m_out_link; diff --git a/src/sim/probe/probe.hh b/src/sim/probe/probe.hh index eb0e445e93..a0bc5689fb 100644 --- a/src/sim/probe/probe.hh +++ b/src/sim/probe/probe.hh @@ -155,7 +155,7 @@ class ProbeManager { private: /** Required for sensible debug messages.*/ - M5_CLASS_VAR_USED const SimObject *object; + GEM5_CLASS_VAR_USED const SimObject *object; /** Vector for name look-up. */ std::vector points;