Merge zizzer.eecs.umich.edu:/bk/newmem/

into  zeep.eecs.umich.edu:/home/gblack/m5/newmemmemops

src/SConscript:
    SCCS merged

--HG--
extra : convert_revision : f130c8a2d33f58d857e5d5a02bb9698c1bceb23b

src/cpu/base.cc

@@ -254,6 +254,26 @@ BaseCPU::regStats()
 #endif
 }
 
+Tick
+BaseCPU::nextCycle()
+{
+    Tick next_tick = curTick + clock - 1;
+    next_tick -= (next_tick % clock);
+    return next_tick;
+}
+
+Tick
+BaseCPU::nextCycle(Tick begin_tick)
+{
+    Tick next_tick = begin_tick;
+
+    while (next_tick < curTick)
+        next_tick += clock;
+
+    next_tick -= (next_tick % clock);
+    assert(next_tick >= curTick);
+    return next_tick;
+}
 
 void
 BaseCPU::registerThreadContexts()

src/cpu/base.hh

@@ -77,6 +77,20 @@ class BaseCPU : public MemObject
     inline Tick cycles(int numCycles) const { return clock * numCycles; }
     inline Tick curCycle() const { return curTick / clock; }
 
+    /** The next cycle the CPU should be scheduled, given a cache
+     * access or quiesce event returning on this cycle.  This function
+     * may return curTick if the CPU should run on the current cycle.
+     */
+    Tick nextCycle();
+
+    /** The next cycle the CPU should be scheduled, given a cache
+     * access or quiesce event returning on the given Tick.  This
+     * function may return curTick if the CPU should run on the
+     * current cycle.
+     * @param begin_tick The tick that the event is completing on.
+     */
+    Tick nextCycle(Tick begin_tick);
+
 #if FULL_SYSTEM
   protected:
 //    uint64_t interrupts[TheISA::NumInterruptLevels];

src/cpu/inst_seq.hh

@@ -32,8 +32,6 @@
 #ifndef __STD_TYPES_HH__
 #define __STD_TYPES_HH__
 
-#include <stdint.h>
-
 // inst sequence type, used to order instructions in the ready list,
 // if this rolls over the ready list order temporarily will get messed
 // up, but execution will continue and complete correctly

src/cpu/o3/lsq_unit_impl.hh

@@ -131,6 +131,7 @@ LSQUnit<Impl>::init(Params *params, LSQ *lsq_ptr, unsigned maxLQEntries,
     usedPorts = 0;
     cachePorts = params->cachePorts;
 
+    retryPkt = NULL;
     memDepViolator = NULL;
 
     blockedLoadSeqNum = 0;

src/cpu/simple/atomic.cc

@@ -180,9 +180,7 @@ AtomicSimpleCPU::resume()
         changeState(SimObject::Running);
         if (thread->status() == ThreadContext::Active) {
             if (!tickEvent.scheduled()) {
-                Tick nextTick = curTick + cycles(1) - 1;
-                nextTick -= (nextTick % (cycles(1)));
-                tickEvent.schedule(nextTick);
+                tickEvent.schedule(nextCycle());
             }
         }
     }
@@ -211,9 +209,7 @@ AtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
         ThreadContext *tc = threadContexts[i];
         if (tc->status() == ThreadContext::Active && _status != Running) {
             _status = Running;
-            Tick nextTick = curTick + cycles(1) - 1;
-            nextTick -= (nextTick % (cycles(1)));
-            tickEvent.schedule(nextTick);
+            tickEvent.schedule(nextCycle());
             break;
         }
     }
@@ -231,9 +227,7 @@ AtomicSimpleCPU::activateContext(int thread_num, int delay)
 
     notIdleFraction++;
     //Make sure ticks are still on multiples of cycles
-    Tick nextTick = curTick + cycles(delay + 1) - 1;
-    nextTick -= (nextTick % (cycles(1)));
-    tickEvent.schedule(nextTick);
+    tickEvent.schedule(nextCycle(curTick + cycles(delay)));
     _status = Running;
 }
 

src/cpu/simple/timing.cc

@@ -532,14 +532,13 @@ TimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt)
 {
     if (pkt->isResponse()) {
         // delay processing of returned data until next CPU clock edge
-        Tick time = pkt->req->getTime();
-        while (time < curTick)
-            time += lat;
+        Tick mem_time = pkt->req->getTime();
+        Tick next_tick = cpu->nextCycle(mem_time);
 
-        if (time == curTick)
+        if (next_tick == curTick)
             cpu->completeIfetch(pkt);
         else
-            tickEvent.schedule(pkt, time);
+            tickEvent.schedule(pkt, next_tick);
 
         return true;
     }
@@ -610,14 +609,13 @@ TimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt)
 {
     if (pkt->isResponse()) {
         // delay processing of returned data until next CPU clock edge
-        Tick time = pkt->req->getTime();
-        while (time < curTick)
-            time += lat;
+        Tick mem_time = pkt->req->getTime();
+        Tick next_tick = cpu->nextCycle(mem_time);
 
-        if (time == curTick)
+        if (next_tick == curTick)
             cpu->completeDataAccess(pkt);
         else
-            tickEvent.schedule(pkt, time);
+            tickEvent.schedule(pkt, next_tick);
 
         return true;
     }