Merge zizzer.eecs.umich.edu:/bk/newmem/

into  zeep.eecs.umich.edu:/home/gblack/m5/newmemmemops

src/SConscript:
    SCCS merged

--HG--
extra : convert_revision : f130c8a2d33f58d857e5d5a02bb9698c1bceb23b

src/arch/sparc/floatregfile.cc

@@ -34,6 +34,8 @@
 #include "sim/byteswap.hh"
 #include "sim/serialize.hh"
 
+#include <string.h>
+
 using namespace SparcISA;
 using namespace std;
 
@@ -55,7 +57,7 @@ string SparcISA::getFloatRegName(RegIndex index)
 
 void FloatRegFile::clear()
 {
-    bzero(regSpace, sizeof(regSpace));
+    memset(regSpace, 0, sizeof(regSpace));
 }
 
 FloatReg FloatRegFile::readReg(int floatReg, int width)

src/arch/sparc/intregfile.cc

@@ -33,6 +33,8 @@
 #include "base/trace.hh"
 #include "sim/serialize.hh"
 
+#include <string.h>
+
 using namespace SparcISA;
 using namespace std;
 
@@ -62,7 +64,7 @@ void IntRegFile::clear()
     for (x = 0; x < MaxGL; x++)
         memset(regGlobals[x], 0, sizeof(IntReg) * RegsPerFrame);
     for(int x = 0; x < 2 * NWindows; x++)
-        bzero(regSegments[x], sizeof(IntReg) * RegsPerFrame);
+        memset(regSegments[x], 0, sizeof(IntReg) * RegsPerFrame);
 }
 
 IntRegFile::IntRegFile()

src/base/pollevent.cc

@@ -30,6 +30,9 @@
 
 #include <sys/ioctl.h>
 #include <sys/types.h>
+#if defined(__sun__)
+#include <sys/file.h>
+#endif
 
 #include <fcntl.h>
 #include <signal.h>

src/base/random.cc

@@ -32,6 +32,10 @@
 #include <cstdlib>
 #include <cmath>
 
+#if defined(__sun__)
+#include <ieeefp.h>
+#endif
+
 #include "sim/param.hh"
 #include "base/random.hh"
 #include "base/trace.hh"
@@ -65,12 +69,27 @@ getLong()
     return mrand48();
 }
 
+double
+m5round(double r)
+{
+#if defined(__sun__)
+    double val;
+    fp_rnd oldrnd = fpsetround(FP_RN);
+    val = rint(r);
+    fpsetround(oldrnd);
+    return val;
+#else
+    return round(r);
+#endif
+}
+
 int64_t
 getUniform(int64_t min, int64_t max)
 {
     double r;
     r = drand48() * (max-min) + min;
-    return (int64_t)round(r);
+
+    return (int64_t)m5round(r);
 }
 
 uint64_t
@@ -78,7 +97,8 @@ getUniformPos(uint64_t min, uint64_t max)
 {
     double r;
     r = drand48() * (max-min) + min;
-    return (uint64_t)round(r);
+
+    return (uint64_t)m5round(r);
 }
 
 

src/base/random.hh

@@ -36,6 +36,7 @@
 
 long getLong();
 double getDouble();
+double m5random(double r);
 uint64_t getUniformPos(uint64_t min, uint64_t max);
 int64_t getUniform(int64_t min, int64_t max);
 

src/base/stats/flags.hh

@@ -36,7 +36,7 @@ namespace Stats {
  * Define the storage for format flags.
  * @todo Can probably shrink this.
  */
-typedef u_int32_t StatFlags;
+typedef uint32_t StatFlags;
 
 /** Nothing extra to print. */
 const StatFlags none =		0x00000000;

src/base/time.hh

@@ -65,4 +65,48 @@ Time operator-(const Time &l, const Time &r);
 
 std::ostream &operator<<(std::ostream &out, const Time &time);
 
+
+/*
+ * Copyright (c) 1982, 1986, 1993
+ *	The Regents of the University of California.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ *	@(#)time.h	8.2 (Berkeley) 7/10/94
+ */
+
+#if defined(__sun__)
+#define timersub(tvp, uvp, vvp)                                         \
+    do {                                                            \
+            (vvp)->tv_sec = (tvp)->tv_sec - (uvp)->tv_sec; \
+            (vvp)->tv_usec = (tvp)->tv_usec - (uvp)->tv_usec;       \
+            if ((vvp)->tv_usec < 0) { \
+                (vvp)->tv_sec--; \
+                (vvp)->tv_usec += 1000000; \
+            } \
+    } while (0)
+#endif
+
 #endif // __SIM_TIME_HH__

src/cpu/base.cc

@@ -254,6 +254,26 @@ BaseCPU::regStats()
 #endif
 }
 
+Tick
+BaseCPU::nextCycle()
+{
+    Tick next_tick = curTick + clock - 1;
+    next_tick -= (next_tick % clock);
+    return next_tick;
+}
+
+Tick
+BaseCPU::nextCycle(Tick begin_tick)
+{
+    Tick next_tick = begin_tick;
+
+    while (next_tick < curTick)
+        next_tick += clock;
+
+    next_tick -= (next_tick % clock);
+    assert(next_tick >= curTick);
+    return next_tick;
+}
 
 void
 BaseCPU::registerThreadContexts()

src/cpu/base.hh

@@ -77,6 +77,20 @@ class BaseCPU : public MemObject
     inline Tick cycles(int numCycles) const { return clock * numCycles; }
     inline Tick curCycle() const { return curTick / clock; }
 
+    /** The next cycle the CPU should be scheduled, given a cache
+     * access or quiesce event returning on this cycle.  This function
+     * may return curTick if the CPU should run on the current cycle.
+     */
+    Tick nextCycle();
+
+    /** The next cycle the CPU should be scheduled, given a cache
+     * access or quiesce event returning on the given Tick.  This
+     * function may return curTick if the CPU should run on the
+     * current cycle.
+     * @param begin_tick The tick that the event is completing on.
+     */
+    Tick nextCycle(Tick begin_tick);
+
 #if FULL_SYSTEM
   protected:
 //    uint64_t interrupts[TheISA::NumInterruptLevels];

src/cpu/inst_seq.hh

@@ -32,8 +32,6 @@
 #ifndef __STD_TYPES_HH__
 #define __STD_TYPES_HH__
 
-#include <stdint.h>
-
 // inst sequence type, used to order instructions in the ready list,
 // if this rolls over the ready list order temporarily will get messed
 // up, but execution will continue and complete correctly

src/cpu/o3/lsq_unit_impl.hh

@@ -131,6 +131,7 @@ LSQUnit<Impl>::init(Params *params, LSQ *lsq_ptr, unsigned maxLQEntries,
     usedPorts = 0;
     cachePorts = params->cachePorts;
 
+    retryPkt = NULL;
     memDepViolator = NULL;
 
     blockedLoadSeqNum = 0;

src/cpu/simple/atomic.cc

@@ -180,9 +180,7 @@ AtomicSimpleCPU::resume()
         changeState(SimObject::Running);
         if (thread->status() == ThreadContext::Active) {
             if (!tickEvent.scheduled()) {
-                Tick nextTick = curTick + cycles(1) - 1;
-                nextTick -= (nextTick % (cycles(1)));
-                tickEvent.schedule(nextTick);
+                tickEvent.schedule(nextCycle());
             }
         }
     }
@@ -211,9 +209,7 @@ AtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
         ThreadContext *tc = threadContexts[i];
         if (tc->status() == ThreadContext::Active && _status != Running) {
             _status = Running;
-            Tick nextTick = curTick + cycles(1) - 1;
-            nextTick -= (nextTick % (cycles(1)));
-            tickEvent.schedule(nextTick);
+            tickEvent.schedule(nextCycle());
             break;
         }
     }
@@ -231,9 +227,7 @@ AtomicSimpleCPU::activateContext(int thread_num, int delay)
 
     notIdleFraction++;
     //Make sure ticks are still on multiples of cycles
-    Tick nextTick = curTick + cycles(delay + 1) - 1;
-    nextTick -= (nextTick % (cycles(1)));
-    tickEvent.schedule(nextTick);
+    tickEvent.schedule(nextCycle(curTick + cycles(delay)));
     _status = Running;
 }
 

src/cpu/simple/timing.cc

@@ -532,14 +532,13 @@ TimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt)
 {
     if (pkt->isResponse()) {
         // delay processing of returned data until next CPU clock edge
-        Tick time = pkt->req->getTime();
-        while (time < curTick)
-            time += lat;
+        Tick mem_time = pkt->req->getTime();
+        Tick next_tick = cpu->nextCycle(mem_time);
 
-        if (time == curTick)
+        if (next_tick == curTick)
             cpu->completeIfetch(pkt);
         else
-            tickEvent.schedule(pkt, time);
+            tickEvent.schedule(pkt, next_tick);
 
         return true;
     }
@@ -610,14 +609,13 @@ TimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt)
 {
     if (pkt->isResponse()) {
         // delay processing of returned data until next CPU clock edge
-        Tick time = pkt->req->getTime();
-        while (time < curTick)
-            time += lat;
+        Tick mem_time = pkt->req->getTime();
+        Tick next_tick = cpu->nextCycle(mem_time);
 
-        if (time == curTick)
+        if (next_tick == curTick)
             cpu->completeDataAccess(pkt);
         else
-            tickEvent.schedule(pkt, time);
+            tickEvent.schedule(pkt, next_tick);
 
         return true;
     }

src/dev/isa_fake.cc

@@ -25,18 +25,13 @@
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
- * Authors: Miguel Serrano
- *          Ali Saidi
+ * Authors: Ali Saidi
  */
 
 /** @file
  * Isa Fake Device implementation
  */
 
-#include <deque>
-#include <string>
-#include <vector>
-
 #include "base/trace.hh"
 #include "dev/isa_fake.hh"
 #include "mem/packet.hh"
@@ -49,74 +44,67 @@ using namespace std;
 IsaFake::IsaFake(Params *p)
     : BasicPioDevice(p)
 {
-    pioSize = p->pio_size;
-}
+    if (!params()->retBadAddr)
+        pioSize = p->pio_size;
 
-Tick
-IsaFake::read(PacketPtr pkt)
-{
-    assert(pkt->result == Packet::Unknown);
-    assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
-
-    DPRINTF(Tsunami, "read  va=%#x size=%d\n", pkt->getAddr(), pkt->getSize());
-
-    switch (pkt->getSize()) {
-      case sizeof(uint64_t):
-         pkt->set(0xFFFFFFFFFFFFFFFFULL);
-         break;
-      case sizeof(uint32_t):
-         pkt->set((uint32_t)0xFFFFFFFF);
-         break;
-      case sizeof(uint16_t):
-         pkt->set((uint16_t)0xFFFF);
-         break;
-      case sizeof(uint8_t):
-         pkt->set((uint8_t)0xFF);
-         break;
-      default:
-        panic("invalid access size(?) for PCI configspace!\n");
-    }
-    pkt->result = Packet::Success;
-    return pioDelay;
-}
-
-Tick
-IsaFake::write(PacketPtr pkt)
-{
-    DPRINTF(Tsunami, "write - va=%#x size=%d \n", pkt->getAddr(), pkt->getSize());
-    pkt->result = Packet::Success;
-    return pioDelay;
-}
-
-BadAddr::BadAddr(Params *p)
-    : BasicPioDevice(p)
-{
+    memset(&retData, p->retData, sizeof(retData));
 }
 
 void
-BadAddr::init()
+IsaFake::init()
 {
     // Only init this device if it's connected to anything.
     if (pioPort)
         PioDevice::init();
 }
 
+
 Tick
-BadAddr::read(PacketPtr pkt)
+IsaFake::read(PacketPtr pkt)
 {
     assert(pkt->result == Packet::Unknown);
-    DPRINTF(Tsunami, "read to bad address va=%#x size=%d\n",
-            pkt->getAddr(), pkt->getSize());
-    pkt->result = Packet::BadAddress;
+
+    if (params()->retBadAddr) {
+        DPRINTF(Tsunami, "read to bad address va=%#x size=%d\n",
+                pkt->getAddr(), pkt->getSize());
+        pkt->result = Packet::BadAddress;
+    } else {
+        assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
+        DPRINTF(Tsunami, "read  va=%#x size=%d\n",
+                pkt->getAddr(), pkt->getSize());
+        switch (pkt->getSize()) {
+          case sizeof(uint64_t):
+             pkt->set(retData);
+             break;
+          case sizeof(uint32_t):
+             pkt->set((uint32_t)retData);
+             break;
+          case sizeof(uint16_t):
+             pkt->set((uint16_t)retData);
+             break;
+          case sizeof(uint8_t):
+             pkt->set((uint8_t)retData);
+             break;
+          default:
+            panic("invalid access size!\n");
+        }
+        pkt->result = Packet::Success;
+    }
     return pioDelay;
 }
 
 Tick
-BadAddr::write(PacketPtr pkt)
+IsaFake::write(PacketPtr pkt)
 {
-    DPRINTF(Tsunami, "write to bad address va=%#x size=%d \n",
-            pkt->getAddr(), pkt->getSize());
-    pkt->result = Packet::BadAddress;
+    if (params()->retBadAddr) {
+        DPRINTF(Tsunami, "write to bad address va=%#x size=%d \n",
+                pkt->getAddr(), pkt->getSize());
+        pkt->result = Packet::BadAddress;
+    } else {
+        DPRINTF(Tsunami, "write - va=%#x size=%d \n",
+                pkt->getAddr(), pkt->getSize());
+        pkt->result = Packet::Success;
+    }
     return pioDelay;
 }
 
@@ -125,6 +113,8 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(IsaFake)
     Param<Addr> pio_addr;
     Param<Tick> pio_latency;
     Param<Addr> pio_size;
+    Param<bool> ret_bad_addr;
+    Param<uint8_t> ret_data;
     SimObjectParam<Platform *> platform;
     SimObjectParam<System *> system;
 
@@ -135,6 +125,8 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(IsaFake)
     INIT_PARAM(pio_addr, "Device Address"),
     INIT_PARAM(pio_latency, "Programmed IO latency"),
     INIT_PARAM(pio_size, "Size of address range"),
+    INIT_PARAM(ret_bad_addr, "Return pkt status BadAddr"),
+    INIT_PARAM(ret_data, "Data to return if not bad addr"),
     INIT_PARAM(platform, "platform"),
     INIT_PARAM(system, "system object")
 
@@ -147,40 +139,11 @@ CREATE_SIM_OBJECT(IsaFake)
     p->pio_addr = pio_addr;
     p->pio_delay = pio_latency;
     p->pio_size = pio_size;
+    p->retBadAddr = ret_bad_addr;
+    p->retData = ret_data;
     p->platform = platform;
     p->system = system;
     return new IsaFake(p);
 }
 
 REGISTER_SIM_OBJECT("IsaFake", IsaFake)
-
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(BadAddr)
-
-    Param<Addr> pio_addr;
-    Param<Tick> pio_latency;
-    SimObjectParam<Platform *> platform;
-    SimObjectParam<System *> system;
-
-END_DECLARE_SIM_OBJECT_PARAMS(BadAddr)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(BadAddr)
-
-    INIT_PARAM(pio_addr, "Device Address"),
-    INIT_PARAM(pio_latency, "Programmed IO latency"),
-    INIT_PARAM(platform, "platform"),
-    INIT_PARAM(system, "system object")
-
-END_INIT_SIM_OBJECT_PARAMS(BadAddr)
-
-CREATE_SIM_OBJECT(BadAddr)
-{
-    BadAddr::Params *p = new BadAddr::Params;
-    p->name = getInstanceName();
-    p->pio_addr = pio_addr;
-    p->pio_delay = pio_latency;
-    p->platform = platform;
-    p->system = system;
-    return new BadAddr(p);
-}
-
-REGISTER_SIM_OBJECT("BadAddr", BadAddr)

src/dev/isa_fake.hh

@@ -25,8 +25,7 @@
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
- * Authors: Miguel Serrano
- *          Ali Saidi
+ * Authors: Ali Saidi
  */
 
 /** @file
@@ -42,10 +41,11 @@
 #include "mem/packet.hh"
 
 /**
- * IsaFake is a device that returns -1 on all reads and
- * accepts all writes. It is meant to be placed at an address range
+ * IsaFake is a device that returns, BadAddr, 1 or 0 on all reads and
+ *  rites. It is meant to be placed at an address range
  * so that an mcheck doesn't occur when an os probes a piece of hw
- * that doesn't exist (e.g. UARTs1-3).
+ * that doesn't exist (e.g. UARTs1-3), or catch requests in the memory system
+ * that have no responders..
  */
 class IsaFake : public BasicPioDevice
 {
@@ -53,9 +53,12 @@ class IsaFake : public BasicPioDevice
     struct Params : public BasicPioDevice::Params
     {
         Addr pio_size;
+        bool retBadAddr;
+        uint8_t retData;
     };
   protected:
     const Params *params() const { return (const Params*)_params; }
+    uint64_t retData;
 
   public:
     /**
@@ -77,23 +80,8 @@ class IsaFake : public BasicPioDevice
      * @param data the data to not write.
      */
     virtual Tick write(PacketPtr pkt);
+
+    void init();
 };
 
-/**
- * BadAddr is a device that fills the packet's result field with "BadAddress".
- * @todo: Consider consolidating with IsaFake and similar classes.
- */
-class BadAddr : public BasicPioDevice
-{
-  public:
-    struct Params : public BasicPioDevice::Params
-    {
-    };
-
-    BadAddr(Params *p);
-    virtual void init();
-    virtual Tick read(PacketPtr pkt);
-    virtual Tick write(PacketPtr pkt);
-};
-
-#endif // __TSUNAMI_FAKE_HH__
+#endif // __ISA_FAKE_HH__

src/python/m5/objects/Pci.py

@@ -57,6 +57,3 @@ class PciDevice(DmaDevice):
     pio_latency = Param.Latency('1ns', "Programmed IO latency in simticks")
     configdata = Param.PciConfigData(Parent.any, "PCI Config data")
     config_latency = Param.Latency('20ns', "Config read or write latency")
-
-class PciFake(PciDevice):
-    type = 'PciFake'

src/python/m5/objects/Tsunami.py

@@ -14,9 +14,11 @@ class TsunamiCChip(BasicPioDevice):
 class IsaFake(BasicPioDevice):
     type = 'IsaFake'
     pio_size = Param.Addr(0x8, "Size of address range")
+    ret_data = Param.UInt8(0xFF, "Default data to return")
+    ret_bad_addr = Param.Bool(False, "Return pkt status bad address on access")
 
-class BadAddr(BasicPioDevice):
-    type = 'BadAddr'
+class BadAddr(IsaFake):
+    ret_bad_addr = Param.Bool(True, "Return pkt status bad address on access")
 
 class TsunamiIO(BasicPioDevice):
     type = 'TsunamiIO'

src/sim/byteswap.hh

@@ -47,6 +47,8 @@
 // If one doesn't exist, we pretty much get what is listed below, so it all
 // works out
 #include <byteswap.h>
+#elif defined (__sun__)
+#include <sys/isa_defs.h>
 #else
 #include <machine/endian.h>
 #endif
@@ -128,12 +130,12 @@ template <typename T> static inline T letobe(T value) {return swap_byte(value);}
 
 //For conversions not involving the guest system, we can define the functions
 //conditionally based on the BYTE_ORDER macro and outside of the namespaces
-#if BYTE_ORDER == BIG_ENDIAN
+#if defined(_BIG_ENDIAN) || BYTE_ORDER == BIG_ENDIAN
 template <typename T> static inline T htole(T value) {return swap_byte(value);}
 template <typename T> static inline T letoh(T value) {return swap_byte(value);}
 template <typename T> static inline T htobe(T value) {return value;}
 template <typename T> static inline T betoh(T value) {return value;}
-#elif BYTE_ORDER == LITTLE_ENDIAN
+#elif defined(_LITTLE_ENDIAN) || BYTE_ORDER == LITTLE_ENDIAN
 template <typename T> static inline T htole(T value) {return value;}
 template <typename T> static inline T letoh(T value) {return value;}
 template <typename T> static inline T htobe(T value) {return swap_byte(value);}