configs: Remove simpleSystem factory function
The function had been introduced in the past when we needed to instantiate either an ArmSystem or a LinuxArmSystem depending on the workload. Now that the workload object has been introduced in gem5, we always instantiate an ArmSystem in FS mode, hence we don't need a function to generate the System object Change-Id: I79ccf31087b84521cce32da71bc835ff202dc432 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43285 Reviewed-by: Jason Lowe-Power <power.jg@gmail.com> Maintainer: Jason Lowe-Power <power.jg@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Giacomo Travaglini
@@ -277,113 +277,105 @@ class FastmodelCluster(SubSystem):
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def connectMemSide(self, bus):
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pass
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def simpleSystem(BaseSystem, caches, mem_size, platform=None, **kwargs):
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"""
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Create a simple system example. The base class in configurable so
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that it is possible (e.g) to link the platform (hardware configuration)
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with a baremetal ArmSystem or with a LinuxArmSystem.
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"""
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class SimpleSystem(BaseSystem):
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cache_line_size = 64
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class SimpleSystem(ArmSystem):
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cache_line_size = 64
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def __init__(self, caches, mem_size, platform=None, **kwargs):
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super(SimpleSystem, self).__init__(**kwargs)
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def __init__(self, caches, mem_size, platform=None, **kwargs):
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super(SimpleSystem, self).__init__(**kwargs)
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self.voltage_domain = VoltageDomain(voltage="1.0V")
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self.clk_domain = SrcClockDomain(
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clock="1GHz",
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voltage_domain=Parent.voltage_domain)
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self.voltage_domain = VoltageDomain(voltage="1.0V")
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self.clk_domain = SrcClockDomain(
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clock="1GHz",
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voltage_domain=Parent.voltage_domain)
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if platform is None:
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self.realview = VExpress_GEM5_V1()
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else:
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self.realview = platform
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if platform is None:
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self.realview = VExpress_GEM5_V1()
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else:
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self.realview = platform
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if hasattr(self.realview.gic, 'cpu_addr'):
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self.gic_cpu_addr = self.realview.gic.cpu_addr
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if hasattr(self.realview.gic, 'cpu_addr'):
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self.gic_cpu_addr = self.realview.gic.cpu_addr
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self.membus = MemBus()
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self.membus = MemBus()
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self.intrctrl = IntrControl()
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self.terminal = Terminal()
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self.vncserver = VncServer()
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self.intrctrl = IntrControl()
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self.terminal = Terminal()
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self.vncserver = VncServer()
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self.iobus = IOXBar()
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# CPUs->PIO
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self.iobridge = Bridge(delay='50ns')
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# Device DMA -> MEM
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mem_range = self.realview._mem_regions[0]
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assert int(mem_range.size()) >= int(Addr(mem_size))
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self.mem_ranges = [
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AddrRange(start=mem_range.start, size=mem_size) ]
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self.iobus = IOXBar()
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# CPUs->PIO
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self.iobridge = Bridge(delay='50ns')
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# Device DMA -> MEM
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mem_range = self.realview._mem_regions[0]
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assert int(mem_range.size()) >= int(Addr(mem_size))
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self.mem_ranges = [
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AddrRange(start=mem_range.start, size=mem_size) ]
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self._caches = caches
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if self._caches:
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self.iocache = IOCache(addr_ranges=[self.mem_ranges[0]])
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else:
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self.dmabridge = Bridge(delay='50ns',
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ranges=[self.mem_ranges[0]])
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self._caches = caches
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if self._caches:
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self.iocache = IOCache(addr_ranges=[self.mem_ranges[0]])
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else:
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self.dmabridge = Bridge(delay='50ns',
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ranges=[self.mem_ranges[0]])
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self._clusters = []
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self._num_cpus = 0
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self._clusters = []
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self._num_cpus = 0
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def attach_pci(self, dev):
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self.realview.attachPciDevice(dev, self.iobus)
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def attach_pci(self, dev):
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self.realview.attachPciDevice(dev, self.iobus)
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def connect(self):
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self.iobridge.mem_side_port = self.iobus.cpu_side_ports
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self.iobridge.cpu_side_port = self.membus.mem_side_ports
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def connect(self):
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self.iobridge.mem_side_port = self.iobus.cpu_side_ports
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self.iobridge.cpu_side_port = self.membus.mem_side_ports
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if self._caches:
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self.iocache.mem_side = self.membus.cpu_side_ports
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self.iocache.cpu_side = self.iobus.mem_side_ports
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else:
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self.dmabridge.mem_side_port = self.membus.cpu_side_ports
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self.dmabridge.cpu_side_port = self.iobus.mem_side_ports
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if self._caches:
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self.iocache.mem_side = self.membus.cpu_side_ports
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self.iocache.cpu_side = self.iobus.mem_side_ports
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else:
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self.dmabridge.mem_side_port = self.membus.cpu_side_ports
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self.dmabridge.cpu_side_port = self.iobus.mem_side_ports
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if hasattr(self.realview.gic, 'cpu_addr'):
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self.gic_cpu_addr = self.realview.gic.cpu_addr
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self.realview.attachOnChipIO(self.membus, self.iobridge)
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self.realview.attachIO(self.iobus)
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self.system_port = self.membus.cpu_side_ports
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if hasattr(self.realview.gic, 'cpu_addr'):
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self.gic_cpu_addr = self.realview.gic.cpu_addr
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self.realview.attachOnChipIO(self.membus, self.iobridge)
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self.realview.attachIO(self.iobus)
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self.system_port = self.membus.cpu_side_ports
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def numCpuClusters(self):
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return len(self._clusters)
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def numCpuClusters(self):
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return len(self._clusters)
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def addCpuCluster(self, cpu_cluster, num_cpus):
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assert cpu_cluster not in self._clusters
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assert num_cpus > 0
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self._clusters.append(cpu_cluster)
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self._num_cpus += num_cpus
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def addCpuCluster(self, cpu_cluster, num_cpus):
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assert cpu_cluster not in self._clusters
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assert num_cpus > 0
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self._clusters.append(cpu_cluster)
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self._num_cpus += num_cpus
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def numCpus(self):
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return self._num_cpus
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def addCaches(self, need_caches, last_cache_level):
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if not need_caches:
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# connect each cluster to the memory hierarchy
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for cluster in self._clusters:
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cluster.connectMemSide(self.membus)
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return
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cluster_mem_bus = self.membus
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assert last_cache_level >= 1 and last_cache_level <= 3
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for cluster in self._clusters:
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cluster.addL1()
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if last_cache_level > 1:
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for cluster in self._clusters:
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cluster.addL2(cluster.clk_domain)
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if last_cache_level > 2:
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max_clock_cluster = max(self._clusters,
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key=lambda c: c.clk_domain.clock[0])
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self.l3 = L3(clk_domain=max_clock_cluster.clk_domain)
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self.toL3Bus = L2XBar(width=64)
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self.toL3Bus.mem_side_ports = self.l3.cpu_side
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self.l3.mem_side = self.membus.cpu_side_ports
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cluster_mem_bus = self.toL3Bus
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def numCpus(self):
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return self._num_cpus
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def addCaches(self, need_caches, last_cache_level):
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if not need_caches:
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# connect each cluster to the memory hierarchy
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for cluster in self._clusters:
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cluster.connectMemSide(cluster_mem_bus)
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cluster.connectMemSide(self.membus)
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return
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return SimpleSystem(caches, mem_size, platform, **kwargs)
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cluster_mem_bus = self.membus
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assert last_cache_level >= 1 and last_cache_level <= 3
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for cluster in self._clusters:
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cluster.addL1()
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if last_cache_level > 1:
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for cluster in self._clusters:
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cluster.addL2(cluster.clk_domain)
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if last_cache_level > 2:
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max_clock_cluster = max(self._clusters,
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key=lambda c: c.clk_domain.clock[0])
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self.l3 = L3(clk_domain=max_clock_cluster.clk_domain)
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self.toL3Bus = L2XBar(width=64)
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self.toL3Bus.mem_side_ports = self.l3.cpu_side
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self.l3.mem_side = self.membus.cpu_side_ports
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cluster_mem_bus = self.toL3Bus
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# connect each cluster to the memory hierarchy
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for cluster in self._clusters:
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cluster.connectMemSide(cluster_mem_bus)
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