dev-amdgpu: Add initial AMDGPU device
The initial device contains enough code for the gpufs configuration scripts to register an amdgpu device that identifies as a Vega 10 (Frontier Edition) device when PCI devices are listed by Linux. It also contains stubs necessary for adding the MMIO interface to handle driver initialization. Using the configuration Linux boots and the device is successfully seen in lspci. The driver can also begin loading an successfully sends initial MMIOs and attempts to read the ROM. Change-Id: I7ad87026876f31f44668e700d5adb639c2c053c1 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44909 Reviewed-by: Jason Lowe-Power <power.jg@gmail.com> Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com> Maintainer: Jason Lowe-Power <power.jg@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>
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Matthew Poremba
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Matt Poremba
Matt Poremba
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233
src/dev/amdgpu/amdgpu_device.cc
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233
src/dev/amdgpu/amdgpu_device.cc
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/*
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* Copyright (c) 2021 Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* For use for simulation and test purposes only
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "dev/amdgpu/amdgpu_device.hh"
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#include <fstream>
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#include "debug/AMDGPUDevice.hh"
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#include "mem/packet.hh"
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#include "mem/packet_access.hh"
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#include "params/AMDGPUDevice.hh"
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#include "sim/byteswap.hh"
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AMDGPUDevice::AMDGPUDevice(const AMDGPUDeviceParams &p)
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: PciDevice(p)
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{
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// Loading the rom binary dumped from hardware.
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std::ifstream romBin;
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romBin.open(p.rom_binary, std::ios::binary);
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romBin.read((char *)rom.data(), ROM_SIZE);
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romBin.close();
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if (config.expansionROM) {
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romRange = RangeSize(config.expansionROM, ROM_SIZE);
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} else {
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romRange = RangeSize(VGA_ROM_DEFAULT, ROM_SIZE);
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}
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}
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void
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AMDGPUDevice::readROM(PacketPtr pkt)
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{
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Addr rom_offset = pkt->getAddr() & (ROM_SIZE - 1);
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uint64_t rom_data = 0;
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memcpy(&rom_data, rom.data() + rom_offset, pkt->getSize());
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pkt->setUintX(rom_data, ByteOrder::little);
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DPRINTF(AMDGPUDevice, "Read from addr %#x on ROM offset %#x data: %#x\n",
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pkt->getAddr(), rom_offset, rom_data);
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}
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AddrRangeList
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AMDGPUDevice::getAddrRanges() const
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{
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AddrRangeList ranges = PciDevice::getAddrRanges();
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AddrRangeList ret_ranges;
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ret_ranges.push_back(romRange);
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// If the range starts at zero assume OS hasn't assigned it yet. Do not
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// return ranges starting with zero as they will surely overlap with
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// another range causing the I/O crossbar to fatal.
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for (auto & r : ranges) {
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if (r.start() != 0) {
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ret_ranges.push_back(r);
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}
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}
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return ret_ranges;
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}
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Tick
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AMDGPUDevice::readConfig(PacketPtr pkt)
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{
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M5_VAR_USED int offset = pkt->getAddr() & PCI_CONFIG_SIZE;
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DPRINTF(AMDGPUDevice, "Read Config: from offset: %#x size: %#x "
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"data: %#x\n", offset, pkt->getSize(), config.data[offset]);
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return PciDevice::readConfig(pkt);
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}
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Tick
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AMDGPUDevice::writeConfig(PacketPtr pkt)
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{
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M5_VAR_USED int offset = pkt->getAddr() & PCI_CONFIG_SIZE;
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DPRINTF(AMDGPUDevice, "Write Config: from offset: %#x size: %#x "
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"data: %#x\n", offset, pkt->getSize(),
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pkt->getUintX(ByteOrder::little));
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return PciDevice::writeConfig(pkt);
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}
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void
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AMDGPUDevice::dispatchAccess(PacketPtr pkt, bool read)
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{
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DPRINTF(AMDGPUDevice, "%s from addr %#x size: %#x data: %#x\n",
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read ? "Read" : "Write", pkt->getAddr(), pkt->getSize(),
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pkt->getUintX(ByteOrder::little));
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pkt->makeAtomicResponse();
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}
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void
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AMDGPUDevice::readFrame(PacketPtr pkt, Addr offset)
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{
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DPRINTF(AMDGPUDevice, "Read framebuffer address %#lx\n", offset);
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}
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void
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AMDGPUDevice::readDoorbell(PacketPtr pkt, Addr offset)
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{
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DPRINTF(AMDGPUDevice, "Read doorbell %#lx\n", offset);
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}
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void
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AMDGPUDevice::readMmio(PacketPtr pkt, Addr offset)
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{
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DPRINTF(AMDGPUDevice, "Read MMIO %#lx\n", offset);
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}
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void
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AMDGPUDevice::writeFrame(PacketPtr pkt, Addr offset)
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{
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DPRINTF(AMDGPUDevice, "Wrote framebuffer address %#lx\n", offset);
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}
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void
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AMDGPUDevice::writeDoorbell(PacketPtr pkt, Addr offset)
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{
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DPRINTF(AMDGPUDevice, "Wrote doorbell %#lx\n", offset);
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}
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void
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AMDGPUDevice::writeMmio(PacketPtr pkt, Addr offset)
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{
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DPRINTF(AMDGPUDevice, "Wrote MMIO %#lx\n", offset);
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}
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Tick
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AMDGPUDevice::read(PacketPtr pkt)
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{
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if (isROM(pkt->getAddr())) {
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readROM(pkt);
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} else {
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int barnum = -1;
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Addr offset = 0;
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getBAR(pkt->getAddr(), barnum, offset);
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switch (barnum) {
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case 0:
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readFrame(pkt, offset);
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break;
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case 2:
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readDoorbell(pkt, offset);
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break;
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case 5:
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readMmio(pkt, offset);
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break;
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default:
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panic("Request with address out of mapped range!");
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}
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}
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dispatchAccess(pkt, true);
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return pioDelay;
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}
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Tick
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AMDGPUDevice::write(PacketPtr pkt)
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{
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int barnum = -1;
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Addr offset = 0;
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getBAR(pkt->getAddr(), barnum, offset);
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switch (barnum) {
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case 0:
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writeFrame(pkt, offset);
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break;
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case 2:
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writeDoorbell(pkt, offset);
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break;
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case 5:
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writeMmio(pkt, offset);
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break;
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default:
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panic("Request with address out of mapped range!");
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}
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// Record only if there is non-zero value, or a value to be overwritten.
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// Reads return 0 by default.
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uint64_t data = pkt->getUintX(ByteOrder::little);
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if (data || regs.find(pkt->getAddr()) != regs.end())
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regs[pkt->getAddr()] = data;
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dispatchAccess(pkt, false);
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return pioDelay;
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}
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void
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AMDGPUDevice::serialize(CheckpointOut &cp) const
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{
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// Serialize the PciDevice base class
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PciDevice::serialize(cp);
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}
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void
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AMDGPUDevice::unserialize(CheckpointIn &cp)
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{
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// Unserialize the PciDevice base class
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PciDevice::unserialize(cp);
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}
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